The selection of the PLL loop filter components begins with a determination of the optimum bandwidth of the PLL. Often this bandwidth is not known at the initial design stage and must be determined empirically based on system performance. In many cases the bandwidth of a PLL is selected based on the minimum phase noise of the PLL output. This is determined by the trade-off between the phase noise that is translated to the output from the input reference and the noise generated internally by the PLL. In input reference dejitter applications, the spectrum of the noise of the input reference is higher than the internal noise of the PLL. In this case the loop bandwidth is set low so the input reference noise is rejected in the PLL loop filter. Conversely, if the noise of the reference is low relative to the PLL internal noise, then the loop gain of the PLL is increased to suppress internal noise, which also extends the PLL bandwidth. An example of this second case is when a clean reference such as a crystal oscillator is to be frequency translated. The bandwidth of a PLL based on a VCXO is typically used for dejittering applications where the bandwidth is set in the range of 10–250Hz to provide attenuation of input reference clock jitter and to take advantage of the low VCXO noise realized by use of a narrow band crystal resonator. Refer to application note AN-849 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.