ODIV is the value of the 8 bit output divider in series with each output pin multiplexer. It is located in the /DIVx (x= [0:4]) as shown in the functional block diagram in the datasheet. 

Users can program the value of the divider. The datasheet mentions the Configuration0 registers at addresses 0x24, 0x27, 0x28, 0x29 and 0x2C for ODIV0, 1, 2, 3 & 4 respectively.

Consider the functional block diagram in the datasheet. Let us consider an example where the PLLC is locked, VCO is running at a frequency of 120MHz and SRC0 selects PLLC for OUT0. If ODIV1 =10 (decimal), then OUT1 will be 12MHz.

There can be up to three configurations associated with each output divider and stored in EEPROM. There is a fourth configuration which is power down.

We highly recommend downloading the VersaClock programming software, select the part and calculate various output frequencies for a given crystal frequency. You can go into Detail View (accessed by the View menu) and see the values of the various registers selected as optimum by the software.

The software can be found on IDT.com by typing VersaClock into the search field and then select Software from the left side bar. At the resulting screen, select the version for your operating system. Alternatively use this link.