Electronic systems continue to increase in complexity and functionality with board space always at a premium. Smaller more dense packages including fine pitch ball-grid arrays (fpBGAs) and chip scale packages have resulted in reduced access to device pins with a possible reduction in test coverage. To gain access to these pins, users are utilizing a combination of test methods to guarantee greater board test coverage. One of these methods is boundary scan testing. Traditional "bed-of-nails" testing uses Automatic Test Equipment (ATEs), which are being augmented and expanded with boundary scan techniques. When using high density packages and complex multi-function/ voltage I/Os like those found on IDT devices, the Boundary Scan Description Language Files (BSDL) proves useful in testing the devices.

BSDL files are generated for every part and package combination of IEEE 1149.1 compatible devices produced by IDT. These files can be used by third party boundary scan tools to generate test vectors and perform the tests.

IDT's BSDL files are checked for 1149.1 compliance. Test patterns are then generated from the BSDL file that include unique tests for every I/O pin. The test patterns include verification of Test-Logic-Reset and TAP controller operation, BYPASS/IDCODE/USERCODE instructions and registers, and pin mapping of the boundary register to every input/output/bidir/clock pin and control cell.