The 8T49N28x family of UFT3G devices has two 17 bit WDCO registers for APLL0 and two for APLL1 (if applicable). The register field is signed two's complement. This means that the max ppm range is:

-[(2^16)-1]*WDCOlsb to +[(2^16)-1]*WDCOlsb
If WDCOlsb = 0.0127ppm, then the WDCO range is:
=-(65535)*0.0127 to (65535)*0.0127
= -832ppm to 832ppm
WDCO “Normal Offset” registers offset the VCO in Normal, Freerun, and Holdover modes. The registers are “live” and take
immediate effect upon update.
WDCO “Holdover Offset” registers offset the VCO only in Holdover mode and only take effect when the “WDCO” bit is enabled.
The “Holdover Offset” is opposite polarity of the “Normal Offset”. For systems that support only single-byte I2C commands,
the “Holdover Offset” can be used to mask intermediate writes.
Refer to application note AN-870 for more details. For other questions not adderssed by the knowledge base, please submit a technical support request.


Title Other Languages Type Format File Size Date
Application Notes & White Papers
AN-870 UFT3G Frequency Tuning Application Note PDF 926 KB