The 82V3399 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, 4E, 4, SMC, EECOption1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet equipment, DWDM and Wireless base station. The device supports several types of input clock sources: recovered clock from Synchronous Ethernet, STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing. The device consists of T0 and T4 paths. The T0 path is a high quality and highly configurable path to provide system clock for node timing synchronization within a SONET / SDH / Synchronous Ethernet network. The T4 path is simpler and less configurable for equipment synchronization. The T4 path locks independently from the T0 path or locks to the T0 path. An input clock is automatically or manually selected for T0 and T4 path. Both the T0 and T4 paths support three primary operating modes: Free-Run, Locked and Holdover. In Free-Run mode, the DPLL refers to the master clock. In Locked mode, the DPLL locks to the selected input clock. In Holdover mode, the DPLL resorts to the frequency data acquired in Locked mode. Whatever the operating mode is, the DPLL gives a stable performance without being affected by operating conditions or silicon process variations. There are 2 high performance APLLs that can be used for low jitter SONET and Ethernet Clocks The device provides programmable DPLL bandwidths: 0.5 mHz to 560 Hz in 19 steps and damping factors: 1.2 to 20 in 5 steps. Different settings cover all SONET / SDH clock synchronization requirements. A highly stable input is required for the master clock in different applications. The master clock is used as a reference clock for all the internal circuits in the device. It can be calibrated within ±741 ppm. All the read/write registers are accessed through a microprocessor interface. The device supports I2C and serial microprocessor interface modes. In general, the device can be used in Master/Slave application. In this application, two devices should be used together to enable system protection against single chip failure.

特長

  • Single chip PLL:
  • Features 0.5 mHz to 560 Hz bandwidth
  • Provides node clock for ITU-T G.8261/G.8262 Synchronous Ethernet (SyncE)
  • Exceeds GR-253-CORE (OC-192) and ITU-T G.813 (STM-64) jitter generation requirements
  • Provides node clocks for Cellular and WLL base-station (GSM and 3G networks)
  • Provides clocks for DSL access concentrators (DSLAM), especially for Japan TCM-ISDN network timing based ADSL equipments
  • Provides clocks for 1 Gigabit and 10 Gigabit Ethernet applications
  • It supports clock generation for IEEE-1588 application
  • Provides an integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, 4E, 4, SMC, EEC-Option 1 and EEC-Option 2 Clocks
  • Provides SONET clocks with less than 1 ps of RMS Phase Jitter (12 kHz - 20 MHz)
  • Supports 1PPS input and output
  • Employs PLL architecture to feature excellent jitter performance and minimize the number of the external components
  • Integrates T0 DPLL and T4 DPLL
  • T4 DPLL locks independently or locks to T0 DPLL
  • Supports programmable DPLL bandwidth (0.5 mHz to 560 Hz in 19 steps) and damping factor (1.2 to 20 in 5 steps)
  • Supports 1.1X10-5 ppm absolute holdover accuracy and 4.4X10-8 ppm instantaneous holdover accuracy
  • Supports hitless reference switching to minimize phase transients on T0 DPLL output to be no more than 0.61 ns
  • Supports programmable input-to-output phase offset adjustment
  • Limits the phase and frequency offset of the outputs
  • Provides OUT1~OUT6 output clocks whose frequencies cover from 1 Hz (1PPS) to 644.53125 MHz
  • Includes 25 MHz, 125 MHz and 156.25 MHz for CMOS outputs
  • Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, for CMOS outputs
  • Includes 25 MHz,125 MHz, 156.25 MHz, 312.5 MHz and 625 MHz for differential outputs
  • Includes 25.78125 MHz, 128.90625 MHz, 161.1328125 MHz, 322.265625 MHz and 644.53125 MHz for differential outputs
  • Provides IN1~IN6 input clocks whose frequencies cover from 1 (1PPS) to 625 MHz
  • Includes 25 MHz, 125 MHz and 156.25 MHz for CMOS inputs
  • Includes 25 MHz, 156.25 MHz, 312.5 MHz and 625 MHz for differential inputs
  • Internal DCO can be controlled by an external processor to be used for IEEE-1588 clock generation
  • Supports Forced or Automatic operating mode switch controlled an internal state machine. It supports Free- Run, Locked and Holdover modes
  • Supports manual and automatic selected input clock switch
  • Supports automatic hitless selected input clock switch on clock failure
  • Supports three types of input clock sources: recovered clock from STM-N or OC-n, PDH network synchronization timing and external synchronization reference timing
  • Provides a 2 kHz, 4 kHz, or 8 kHz frame sync input signal, and kHz or 8 kHz frame sync output signal
  • Provides a 1PPS sync input signal and a 1PPS sync output signal
  • Provides output clocks for BITS, GPS, 3G, GSM, etc.
  • Supports PECL/LVDS and CMOS input/output technologies
  • Supports master clock calibration
  • Supports Master/Slave application (two chips used together) enable system protection against single chip failure
  • Supports Telcordia GR-1244-CORE, Telcordia GR-253-CORE, ITU-T G.812, ITU-T G.8262. ITU-T G.813 and ITU-T G.783 recommendations
  • I2C and Serial microprocessor interface modes
  • IEEE 1149.1 JTAG Boundary Scan
  • Single 3.3 V operation with 5 V tolerant CMOS I/Os
  • 72-pin QFN package, green package options available

製品選択

発注型名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Active VFQFPN 72 C はい Tray
Availability
Active VFQFPN 72 C はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
82V3399 Short Form Data Sheet ショートフォーム(簡略版) PDF 138 KB
82V3399 Data Sheet データシート PDF 1.03 MB
アプリケーションノート、ホワイトペーパー
AN-807 Recommended Crystal Oscillators for Network Synchronization アプリケーションノート PDF 148 KB
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations アプリケーションノート PDF 115 KB
AN-839 RMS Phase Jitter アプリケーションノート PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-806 Power Supply Noise Rejection アプリケーションノート PDF 438 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 製品変更通知 PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 製品変更通知 PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 製品変更通知 PDF 544 KB
PCN# : A1311-03R1 Alternate Assembly Locations 製品変更通知 PDF 43 KB
PCN# : A1311-03 Alternate Assembly Locations 製品変更通知 PDF 140 KB
PCN# : A1308-01 Add ASEK as Alternate Assembly for VFQFPN-72 製品変更通知 PDF 103 KB
その他資料
Timing Fabric for Communications Equipment Overview 概要 PDF 263 KB