The 83940 is a low skew, 1-to-18 LVPECL-to-LVCMOS/ LVTTL Fanout Buffer. The 83940 has twoselectable clock inputs. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The LVCMOS_CLK can accept LVCMOS or LVTTL input levels. The low impedance LVCMOS/LVTTL outputs are designed to drive 50Ω series or parallel terminated transmission lines. The 83940 is characterized at full 3.3V, full 2.5V and mixed 3.3V input and 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 83940 ideal for those clock distribution applications demanding well defined performance and repeatability.

特長

  • Eighteen LVCMOS/LVTTL outputs, 16Ω typical output impedance
  • Selectable LVCMOS_CLK or LVPECL clock inputs
  • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
  • LVCMOS_CLK accepts the following input levels: LVCMOS or LVTTL
  • Maximum output frequency: 250MHz
  • Output skew: 150ps (maximum)
  • Part to part skew: 750ps (maximum)
  • Full 3.3V or 2.5V supply modes
  • 0°C to 70°C ambient operating temperature
  • Industrial temperature information available upon request
  • Lead-Free package fully RoHS compliant
  • NRND - Not Recommended for New Designs 
  • For new designs use 83940D

製品選択

発注型名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type パッケージ 購入/サンプル
83940BYLF Obsolete TQFP 32 C はい Tray Package Info
Availability
83940BYLFT Obsolete TQFP 32 C はい Reel Package Info
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN / PDN
PDN# : CQ-14-02R2 Product Discontinuation Notice PDF 549 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB
PDN# : CQ-14-02R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 545 KB
PDN# : CQ-14-02 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 544 KB
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 Product Change Notice PDF 472 KB
その他資料
IDT Clock Distribution Overview (Japanese) English Overview PDF 7.79 MB
IDT Clock Distribution Overview (Japanese) English Overview PDF 7.79 MB