The 8A34046 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) and Optical Transport Network (OTN) is a highly integrated timing device with four Digital PLL (DPLL) channels and four Digitally Controlled Oscillator (DCO) channels. The device integrates the timing blocks necessary to implement the SETS function as described in ITU-T G.8264.

The 8A34046 DPLL channels can be configured to comply with ITU-T G.8262 and G.8262.1 or as jitter attenuators; they can also be configured as DCOs. The DCO channels can be connected to a DPLL channel to supply additional outputs and frequencies for that DPLL; alternatively they can be controlled by external software or they can free run based on the local oscillator. The device can be used as a single timing and synchronization source for a system or two of them can be used as a redundant pair for improved system reliability. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.

Features

  • Four independent Digital PLLs (DPLLs) and four independent Digitally Controlled Oscillators (DCOs)
  • DPLLs comply with ITU-T G.8262 and G.8262.1 for SyncE and OTN
  • DPLLs lock to any frequency from 1kHz to 1GHz
  • DPLLs / DCOs generate any frequency from 0.5Hz to 1GHz
  • Jitter output below 150fs RMS (typical)
  • Supports up to 4 differential; or 8 single-ended reference clock inputs
  • Supports up to 12 differential outputs; or 24 LVCMOS outputs
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Serial processor ports support 1MHz I2C or 50MHz SPI
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port

Product Options

注文可能な製品ID Part Status Pkg. Code Temp. Range Carrier Type 購入/サンプル
8A34046E-000NLG Active NLG72P4 0 to 70°C Tray
Availability
8A34046E-000NLG8 Active NLG72P4 0 to 70°C Reel
Availability
8A34046E-000NLG# Active NLG72P4 0 to 70°C Reel
Availability

Documentation & Downloads

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
8A34046E-001 Datasheet Addendum Datasheet PDF 100 KB
8A34046 Datasheet Datasheet - Advance PDF 1.24 MB
8A3xxxx Family Errata (Rev B with Update v4.7) Errata PDF 127 KB
ユーザーガイド
8A34xxx 72QFN EVK User Manual Manual - Eval Board PDF 2.03 MB
ClockMatrix GUI Step-by-Step User Guide Guide PDF 4.98 MB
8A3xxxx Family Programming Guide (v4.7) Guide PDF 3.59 MB
アプリケーションノート、ホワイトペーパー
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment Application Note PDF 976 KB
AN-1020 ClockMatrix on nCXO Redundancy Application Note PDF 659 KB
AN-1010 ClockMatrix Time-to-Digital Converter Application Note PDF 1.63 MB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 324 KB
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 164 KB
PCN / PDN
PCN#: TP1902-02 ROM Update for ClockMatrix Products Product Change Notice PDF 435 KB
Downloads
Timing Commander Installer (v1.15.0.27471) Software ZIP 19.57 MB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 Software ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 Software ZIP 177 KB
ClockMatrix Register Header Files v4.7 Software ZIP 293 KB
8A340xx Clock Matrix IBIS Model Model - IBIS ZIP 2.40 MB
その他資料
8A3x0xx Schematic Checklist (v1.22) Miscellaneous XLSX 328 KB
ClockMatrix Family Overview Overview PDF 241 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
ClockMatrix 72-QFN (12 Output) Reference Schematic Schematic PDF 98 KB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB

Boards & Kits