NOTICE - The following device(s) are recommended alternatives:
The 9DB833 zero-delay buffer supports PCIe Gen3 requirements, while being backwards compatible to PCIe Gen2 and Gen1. The 9DB833 is driven by a differential SRC output pair from an IDT 932S421 or 932SQ420 or equivalent main clock generator.
特長
- Eight 0.7V HCSL differential output pairs
- Phase jitter: PCIe Gen3 < 1ps rms
- Phase jitter: PCIe Gen2 < 3.1ps rms
- Phase jitter: PCIe Gen1 < 86ps peak to peak
- Supports zero delay buffer mode and fanout mode
- Bandwidth programming available
- 3 selectable SMBus Addresses
- 50-110 MHz operation in PLL mode
- 5-166 MHz operation in Bypass mode