The 9DBL0651 device is a 3.3V member of IDT's Full-Featured PCIe family. The 9DBL0651 supports PCIe Gen1-4 Common Clocked (CC) and  PCIe Separate Reference Independent Spread (SRIS) systems. It offers an integrated output termination providing direct connection to 85Ω transmission lines. The 9DBL06P1 can be factory programmed with a user-defined power up default SMBus configuration.

For information regarding evaluation boards and material, please contact your local IDT sales representative.

Features

  • PCIe Gen1-2-3-4 CC compliant in ZDB mode
  • PCIe Gen2 SRIS compliant in ZDB mode
  • Supports PCIe Gen2-3 SRIS in fan-out mode
  • Supports PCIe SRnS clocking in ZDB or fan-out mode
  • Direct connection to 85Ω transmission lines; saves 24 resistors compared to standard PCIe devices
  • Spread Spectrum tolerant; allows reduction of EMI
  • Pin/SMBus selectable selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Device contains default configuration; SMBus interface not required for device operation.
  • Easy AC-coupling to other logic families, see IDT application note AN-891.
  • Space saving 40-pin 5x5mm VFQFPN; minimal board space

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type 購入/サンプル
9DBL0651BKILF Active NDG40P2 VFQFPN 40 I , 85 Tray
Availability

購入/見積
9DBL0651BKILFT Active NDG40P2 VFQFPN 40 I , 85 Reel
Availability
購入/見積

技術資料

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
9DBL0641_51 Datasheet – Datasheet PDF 395 KB
ユーザーガイド
Timing Products for NXP (Freescale) i.MX 简体中文 Guide PDF 321 KB
アプリケーションノート、ホワイトペーパー
AN-975 Cascading PLLs – Application Note PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT?s ?Universal? Low-Power HCSL Outputs – Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements – Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 442 KB
AN-839 RMS Phase Jitter – Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels – Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced – Application Note PDF 160 KB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance – Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads – Application Note PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – Product Change Notice PDF 983 KB
その他資料
PCI Express Timing Solutions Overview – Overview PDF 275 KB
9DBL06xx Reference Schematic – Schematic PDF 118 KB
Timing Solutions Products Overview – Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB

ソフトウェア／ツール

タイトル 他の言語 タイプ 形式 サイズ 日付
9DBL06P1 IBIS Model – Model - IBIS ZIP 118 KB
9DBL0641 IBIS Model – Model - IBIS ZIP 89 KB
info: For device-specific or order-specific documentation, submit a support request.

News & Additional Resources

日付
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications 2018年5月21日
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices 2018年4月30日
An Insider’s Guide to Finding the Right Timing Device for Your System 2017年12月18日
Why Fanout Buffers Make More Sense 2017年11月28日
Time for Performance 2017年10月11日
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped 2014年12月18日