The 9DBU0931 is a member of IDT's 1.5 V Ultra-Low-Power (ULP) PCIe family. The device has 5 output enables for clock management, and 3 selectable SMBus addresses.

Features

  • LP-HCSL outputs; save 18 resistors compared to standard HCSL outputs.
  • 47 mW typical power consumption in PLL mode; minimal power consumption
  • Separate power rail for LP-HCSL outputs can optionally be supplied from any voltage between 1.05 and 1.5 V; maximum power savings
  • OE# pin for each output; support DIF power management
  • HCSL differential input; can be driven by common clock sources
  • Spread spectrum tolerant; allows reduction of EMI
  • Programmable Slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • 1 MHz to 167 MHz operating frequency
  • Device contains default configuration; SMBus interface not required for device operation
  • 3.3 V tolerant SMBus interface  works with legacy controllers
  • Selectable SMBus addresses; multiple devices can easily share an SMBus segment
  • Space-saving 6x6 mm 48-pin VFQFPN; minimal board space

Product Options

注文可能な製品ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
9DBU0931AKILF Active NDG48P1 VFQFPN 48 I Yes Tray
Availability

購入/見積
9DBU0931AKILFT Active NDG48P1 VFQFPN 48 I Yes Reel
Availability
購入/見積
9DBU0931AKLF Active NDG48P1 VFQFPN 48 C Yes Tray
Availability

購入/見積
9DBU0931AKLFT Active NDG48P1 VFQFPN 48 C Yes Reel
Availability
購入/見積

Documentation & Downloads

タイトル 他の言語 タイプ 形式 サイズ 日付
データシート
9DBU0931 Datasheet – Datasheet PDF 299 KB
アプリケーションノート、ホワイトペーパー
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT?s ?Universal? Low-Power HCSL Outputs – Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers – Application Note PDF 170 KB
AN-843 PCI Express Reference Clock Requirements – Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 442 KB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads – Application Note PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – Product Change Notice PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location – Product Change Notice PDF 583 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages – Product Change Notice PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages – Product Change Notice PDF 50 KB
その他資料
PCI Express Timing Solutions Overview – Overview PDF 275 KB
Timing Solutions Products Overview – Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview – Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief – Product Brief PDF 378 KB
info: For device-specific or order-specific documentation, submit a support request.

Boards & Kits

News & Additional Resources

日付
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications 2018年5月21日
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices 2018年4月30日
An Insider’s Guide to Finding the Right Timing Device for Your System 2017年12月18日
Why Fanout Buffers Make More Sense 2017年11月28日
Time for Performance 2017年10月11日
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped 2014年12月18日
IDT社、業界トップクラスの省スペース・省電力を実現する 1.5V PCI Express®クロック・バッファ製品を発表 2014年8月5日