The 8SLVD1204 is a high-performance differential LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD1204 is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD1204 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and four low skew outputs are available. The integrated bias voltage reference enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.
 
For a 3.3 V version of this device, please refer to the 8SLVD1204-33I.

Features

  • Four low skew, low additive jitter LVDS output pairs
  • Two selectable differential clock input pairs
  • Differential PCLK, nPCLK pairs can accept the following differential input levels: LVDS, LVPECL
  • Maximum input clock frequency: 2GHz 
  • LVCMOS/LVTTL interface levels for the control input select pin 
  • Output skew: 20ps (maximum)
  • Propagation delay: 300ps (maximum)
  • Low additive phase jitter, RMS; fREF = 156.25MHz, VPP = 1V, 10kHz - 20MHz: 95fs (maximum)
  • Full 2.5V supply voltage
  • Lead-free (RoHS 6), 16-Lead VFQFN packaging
  • -40°C to 85°C ambient operating temperature

Product Options

注文可能な製品ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type パッケージ 購入/サンプル
8SLVD1204NLGI Active VFQFPN 16 I はい Tube Package Info
Availability
8SLVD1204NLGI/W Active VFQFPN 16 I はい Reel Package Info
Availability
8SLVD1204NLGI8 Active VFQFPN 16 I はい Reel Package Info
Availability

Documentation & Downloads

タイトル 他の言語 Type 形式 サイズ 日付
データシート
8SLVD1204 Datasheet Datasheet PDF 491 KB
アプリケーションノート、ホワイトペーパー
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN / PDN
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel
Product Change Notice PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel
Product Change Notice PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility Product Change Notice PDF 983 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
Downloads
8SLVD1204I IBIS Model Model - IBIS ZIP 34 KB
その他資料
RF Timing Family Product Overview Overview PDF 464 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications (日本語) English Product Brief PDF 2.34 MB
IDT Products for Radio Applications (日本語) English Product Brief PDF 2.34 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB