The 524S is a low skew, single input to four output, LVCMOS clock buffer. The 524S has best in class additive phase Jitter of sub 50 fsec.

Features

  • Low additive phase jitter RMS: 50fs
  • Extremely low skew outputs (50ps)
  • Low cost clock buffer
  • Packaged in 8-SOIC and 8-DFN, Pb-free
  • Input / Output clock frequency up to 200MHz
  • Non-inverting output clock
  • Ideal for networking clocks
  • Operating voltages: 1.8V to 3.3V
  • Advanced, low power CMOS process
  • Extended temperature range (-40°C to +105°C)

Product Options

注文可能な製品ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type パッケージ 購入/サンプル
524SCMGI Active COL 8 I Yes Cut Tape Package Info
Availability
524SCMGI8 Active COL 8 I Yes Reel Package Info
Availability
524SDCGI Active SOIC 8 I Yes Tube Package Info
Availability
524SDCGI8 Active SOIC 8 I Yes Reel Package Info
Availability

Documentation & Downloads

タイトル 他の言語 Type 形式 サイズ 日付
データシート
524S Datasheet Datasheet PDF 263 KB
アプリケーションノート、ホワイトペーパー
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
PCN / PDN
PCN# : A1905-02 Adding Carsem, Malaysia as Alternate Assembly Location & Change Material Sets Product Change Notice PDF 268 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
Downloads
524S IBIS Model Model - IBIS ZIP 24 KB
その他資料
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview (日本語) English Overview PDF 1.83 MB
IDT Clock Distribution Overview (日本語) English Overview PDF 3.79 MB