NOTICE - The following device(s) are recommended alternatives:

The 854S1208I is a low skew, 8 output LVDS Fanout Buffer with selectable divider. The 854S1208I has 2 selectable inputs that accept a variety of differential input types. The device provides the capability to suppress any glitch at the outputs of the device during an input clock switch to enhance clock redundancy in fault tolerant applications. The divide select inputs, DIV_SELA and DIV_SELB, control the output frequency of each bank. The output banks can be independently selected for ÷1 or ÷2 operation. The output enable pins assigned to each output, support enabling and disabling each output individually. The 854S1208I is characterized at full 3.3V or 2.5V output operating supply modes. Guaranteed output and part-to-part skew characteristics make the 854S1208I ideal for high performance applications.

特長

  • Eight differential LVDS output pairs Each output has individual synchronous output enable
  • Two selectable differential CLKx, nCLKx input pairs
  • CLKx, nCLKx pairs can accept the following differential input levels: LVPECL, LVDS, HCSL
  • Maximum output frequency: 1.5GHz
  • Independent bank control for ÷1 or ÷2 operation
  • Glitchless output behavior during input switch
  • Output skew: 40ps (maximum)
  • Bank skew: 35ps (maximum)
  • Full 3.3V or 2.5V supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

製品選択

発注型名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete PTQFP 48 I はい Tray
Availability
Obsolete PTQFP 48 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
854S1208I データシート PDF 1.46 MB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PDN# : CQ-17-04(R1) Product Discontinuance Notice 製品中止通知 PDF 606 KB
PCN# : A1709-02 Add alternate assembly at OSET and Convert to Copper Wire 製品変更通知 PDF 35 KB
PDN# : CQ-17-04 Product Discontinuance Notice 製品中止通知 PDF 599 KB
PCN# : A1309-01 Changed of Traceability Mark Format 製品変更通知 PDF 439 KB
その他資料
Timing Solutions Products Overview 概要 PDF 4.11 MB
IDT Products for Radio Applications (Japanese) English 製品概要 PDF 6.27 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB