The 8T39S10I is a high-performance clock fanout buffer. The input clock can be selected from two differential inputs or one crystal input. The internal oscillator circuit is automatically disabled if the crystal input is not selected. The crystal pin can be driven by single-ended clock when crystal is bypassed.The selected signal is distributed to ten differential outputs which can be configured as LVPECL, LVDS or HSCL outputs. In addition, an LVCMOS output is provided. All outputs can be disabled into a high-impedance state. The device is designed for signal fanout of high-frequency, low phase-noise clock and data signal. The outputs are at a defined level when inputs are open circuit or tied to ground. It is designed to operate from a 3.3V or 2.5V core power supply, and either a 3.3V or 2.5V output operating supply.

特長

  • Two differential reference clock input pairs
  • Differential input pairs can accept the following differential input levels: LVPECL, LVDS, HCSL
  • Crystal Oscillator Interface
  • Crystal input frequency range: 10MHz to 40MHz
  • Maximum Output Frequency
    • LVPECL - 2GHz
    • LVDS - 2GHz
    • HCSL - 250MHz
    • LVCMOS - 250MHz
  • Two banks, each has five differential output pairs that can be configured as LVPECL or LVDS or HCSL
  • One single-ended reference output with synchronous enable to avoid clock glitch
  • Output skew: (Bank A and Bank B at the same output level: 70ps (max)
  • Part-to-part skew: 250ps (max)
  • Additive RMS phase jitter: 0.153ps (typical)
  • Supply voltage modes:
    • VDD/VDDO
    • 3.3V/3.3V
    • 3.3V/2.5V
    • 2.5V/2.5V
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging

製品選択

発注型名 Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete 48 I はい Tray
Availability
Obsolete 48 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
8T39S10I Data Sheet データシート PDF 1.08 MB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-846 Termination - LVDS アプリケーションノート PDF 133 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PDN# : CQ-17-02R1 Quarterly Market Declined PDN (revision1) 製品中止通知 PDF 647 KB
PDN# : CQ-17-02 Quarterly Market Declined PDN 製品中止通知 PDF 898 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 製品変更通知 PDF 583 KB
その他資料
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
Timing Solutions Products Overview 概要 PDF 4.11 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB