The 8752I is a low voltage, low skew LVCMOS clock generator. With output up to 240MHz, the 8752I is targeted for high performance clock applications. Along with a fully integrated PLL, the 8752I contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".

Dual clock inputs, CLK0 and CLK1, support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively.

For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When HIGH, the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state.

The low impedance LVCMOS outputs of the 8752I are designed to drive terminated transmission lines. The effective fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated transmission lines.

特長

  • Fully integrated PLL
  • 8 LVCMOS outputs, 7Ω typical output impedance
  • Selectable LVCMOS CLK0 or CLK1 inputs for redundant clock applications
  • Input/Output frequency range: 18.33MHz to 240MHz at VCC = 3.3V ± 5%
  • VCO range: 220MHz to 480MHz
  • External feedback for "zero delay" clock regeneration
  • Cycle-to-cycle jitter: 75ps (maximum), (all outputs are the same frequency)
  • Output skew: 100ps (maximum)
  • Bank skew: 55ps (maximum)
  • Full 3.3V or 2.5V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Lead-Free package fully RoHS compliant

製品選択

発注型名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete TQFP 32 I はい Tray
Availability
Obsolete TQFP 32 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
8752I Datasheet データシート PDF 267 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PDN# : CQ-16-02 Quarter PDN for Declined Market 製品中止通知 PDF 592 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 製品変更通知 PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 製品変更通知 PDF 50 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site 製品変更通知 PDF 36 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 製品変更通知 PDF 472 KB
Downloads
8752I IBIS Model モデル-IBIS ZIP 67 KB
その他資料
Timing Solutions Products Overview 概要 PDF 4.11 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB