The 87972I-147 is a low skew, LVCMOS/LVTTL Clock Generator and a member of the family of High Performance Clock Solutions from IDT. The 87972I-147 has three selectable inputs and provides 14 LVCMOS/LVTTL outputs. The 87972I-147 is a highly flexible device. Using the crystal oscillator input, it can be used to generate clocks for a system. All of these clocks can be the same frequency or the device can be configured to generate up to three different frequencies among the three output banks. Using one of the single ended inputs, the 87972I-147 can be used as a zero delay buffer/multiplier/ divider in clock distribution applications. The three output banks and feedback output each have their own output dividers which allows the device to generate a multitude of different bank frequency ratios and output-to-input frequency ratios. In addition, 2 outputs in Bank C (QC2, QC3) can be selected to be inverting or non-inverting. The output frequency range is 10MHz to 150MHz. Input frequency range is 6MHz to 150MHz. The 87972I-147 also has a QSYNC output which can be used or system synchronization purposes. It monitors Bank A and Bank C outputs and goes low one period of the faster clock prior to coincident rising edges of Bank A and Bank C clocks. QSYNC then goes high again when the coincident rising edges of Bank A and Bank C occur. This feature is used primarily in applications where Bank A and Bank C are running at different frequencies, and is particularly useful when they are running at non-integer multiples of one another.

特長

  • Fully integrated PLL
  • Fourteen LVCMOS/LVTTL outputs
  • (12)clocks, (1)feedback, (1)sync
  • Selectable crystal oscillator interface or LVCMOS/LVTTL reference clock inputs
  • CLK0, CLK1 can accept the following input levels: LVCMOS or LVTTL
  • Output frequency range: 10MHz to 150MHz
  • VCO range: 240MHz to 500MHz
  • Output skew: 200ps (maximum)
  • Cycle-to-cycle jitter, (all banks ÷4): 55ps (maximum)
  • Full 3.3V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Compatible with PowerPC™ and Pentium™ Microprocessors
  • Available in lead-free (RoHS 6) package

製品選択

発注型名 Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Obsolete TQFP 52 I はい Tray
Availability
Obsolete TQFP 52 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
87972I-147 Datasheet データシート PDF 306 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-845 Termination - LVCMOS アプリケーションノート PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced アプリケーションノート PDF 160 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PDN# : CQ-19-01(R1) Quarterly Market Declined PDN 製品中止通知 PDF 1014 KB
PDN# : CQ-19-01 Quarterly Market Declined PDN 製品中止通知 PDF 537 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site 製品変更通知 PDF 36 KB
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE 製品中止通知 PDF 363 KB
Downloads
87972I-147 IBIS Model モデル-IBIS ZIP 6 KB
その他資料
Timing Solutions Products Overview 概要 PDF 4.11 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB