The 8A34044 Multichannel Digital PLL / Digitally Controlled Oscillator (DPLL/DCO) provides tools to manage timing references, clock conversion and timing paths for common communications protocols such as: Synchronous Ethernet (SyncE), Optical Transport Network (OTN) and Common Public Radio Interface (CPRI).  The device can be used to synchronize communication ports on line cards or daughter cards that are connected with synchronization sources across backplanes or other media. Digitally Controlled Oscillators (DCOs) are available to be controlled by OTN clock recovery servo software running on an external processor. Digital PLLs (DPLLs) support filtering of gapped clocks for OTN; and hitless reference switching between references from redundant timing sources. The device supports multiple independent timing channels for: clock generation; jitter attenuation and universal frequency translation.  Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed.  The device outputs ultra-low-jitter clocks that can directly synchronize SERDES running at up to 28Gbps; as well as CPRI/OBSAI, SONET/SDH and PDH interfaces.

To see other devices in this product family, visit the ClockMatrix Timing Solutions page.

特長

  • Two independent Digital PLLs (DPLLs)
  • Six independent Digitally Controlled Oscillators (DCOs)
  • Jitter output below 150fs RMS (typical)
  • DPLLs lock to any frequency from 1kHz to 1GHz
  • DPLLs / DCOs generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • Supports up to 2 differential or 4 single-ended reference clock inputs
  • Supports up to 12 differential outputs or 24 LVCMOS outputs
  • Reference monitors qualify/disqualify references depending on LOS, activity, frequency monitoring and/or LOS input pins
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive / non-revertive and other programmable settings
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Optional XO_DPLL input allows a wider range for XO, TCXO or OCXO frequencies from 1MHz to 150MHz for applications that require a local oscillator with high stability
  • Serial processor ports support 1MHz I2C or 50MHz SPI
  • The device can configure itself automatically after reset via:
    • Internal Customer-programmable One-Time Programmable memory 
    • Standard external I2C EPROM via separate I2C Master Port

製品選択

発注型名 Part Status Temp. Range Carrier Type 購入/サンプル
Active -40 to 85°C Reel
Availability
Active -40 to 85°C Reel
Availability
Active -40 to 85°C Tray
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
8A34044 Datasheet データシート PDF 2.16 MB
8A3xxxx Firmware Version v4.8.7 Errata Notice エラッタ PDF 44 KB
8A3xxxx Family Errata (Rev B with Update v4.7) エラッタ PDF 127 KB
ユーザーガイド
8A3xxxx Family Programming Guide (v4.8.7) ガイド PDF 2.33 MB
8A3xxxx Firmware Version 4.8.7 Release Notes ガイド PDF 101 KB
8A3xxxx Family Programming Guide (v4.8) ガイド PDF 3.60 MB
8A34xxx 72QFN EVK User Manual マニュアル-評価ボード PDF 2.03 MB
ClockMatrix GUI Step-by-Step User Guide ガイド PDF 4.98 MB
アプリケーションノート、ホワイトペーパー
Aligning 1PPS Clocks in Larger Chassis Systems アプリケーションノート PDF 1.62 MB
AN-807 Recommended Crystal Oscillators for Network Synchronization アプリケーションノート PDF 148 KB
AN-1010 ClockMatrix Time-to-Digital Converter アプリケーションノート PDF 1.57 MB
Mapping Clock Device Pins to Clock Numbers in the 8A34001 アプリケーションノート PDF 390 KB
Translating Non-Integer Frequencies with ClockMatrix アプリケーションノート PDF 880 KB
Auto-Alignment of Outputs アプリケーションノート PDF 584 KB
Locking a ClockMatrix DPLL to Internal Feedback アプリケーションノート PDF 155 KB
AN-1030 CM Input/Input-to-Output/Output Phase Adjustment アプリケーションノート PDF 976 KB
AN-1020 ClockMatrix on nCXO Redundancy アプリケーションノート PDF 659 KB
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment アプリケーションノート PDF 324 KB
PCN / PDN
PCN# : TP2002-01 Firmware Update from v4.8 to v4.8.7 製品変更通知 PDF 301 KB
PCN# : TP1906-05 Correct System APLL Loss-of-Lock Issue 製品変更通知 PDF 123 KB
PCN#: TP1902-02 ROM Update for ClockMatrix Products 製品変更通知 PDF 435 KB
Downloads
Timing Commander Installer (v1.16.3) ソフトウェア ZIP 19.85 MB
Timing Commander Personality File for ClockMatrix 8A340xx (v8.4.1, FWv4.8.7) ソフトウェア TCP 46.94 MB
ClockMatrix Register Header Files v4.8.7 ソフトウェア ZIP 278 KB
8A340xx ClockMatrix IBIS Model モデル-IBIS ZIP 2.40 MB
8A34044 BSDL Model モデル-BSDL ZIP 2 KB
EEPROM_Image_PR4.7_Part=24xx1025_Address=0x50-0x54 ソフトウェア ZIP 177 KB
EEPROM_Image_PR4.7_Part=24xx1024_Address=0x50-0x51 ソフトウェア ZIP 177 KB
その他資料
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
8A3x0xx Schematic Checklist (v1.22) その他 XLSX 328 KB
ClockMatrix Family Overview 概要 PDF 241 KB
Timing Solutions Products Overview 概要 PDF 4.11 MB
ClockMatrix 72-QFN (12 Output) Reference Schematic 回路図 PDF 98 KB
IDT Products for Radio Applications (Japanese) English 製品概要 PDF 6.27 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB

ボード&キット

製品名 タイトル 分類 会社名
8A34044-EVK Evaluation Kit for 8A34044 ClockMatrix