Along with CSPUA877A or 98ULPA877A DDR2 PLL Provides a fully JEDEC compliant solution for DDR2 RDIMMs for 400, 533, 667 and 800MHz.

Features

  • 28-bit 1:2 registered buffer with parity check functionality
  • Supports SSTL_18 JEDEC specification on data inputs and outputs
  • Supports LVCMOS switching levels on CSGateEN and RESET inputs
  • Low voltage operation: VDD = 1.7V to 1.9V

Product Options

注文可能な製品ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type パッケージ 購入/サンプル
74SSTUBF32865ABKG Active CABGA 160 C 1 Tray Package Info
Availability
74SSTUBF32865ABKG8 Active CABGA 160 C 1 Reel Package Info
Availability

Documentation & Downloads

タイトル 他の言語 Type 形式 サイズ 日付
データシート
74SSTUBF32865A Datasheet Datasheet PDF 492 KB
PCN / PDN
PCN# : A1604-01 Add OSET Taiwan as Alternate Assembly Product Change Notice PDF 31 KB