Low skew, low jitter PLL clock driver; 1 to 5 differential clock distribution (SSTL_18)

Features

  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Auto PD when input signal is at a certain logic state

Product Options

注文可能な製品ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type パッケージ 購入/サンプル
97ULP845AHILF Active CABGA 28 I Yes Tray Package Info
Availability
97ULP845AHILFT Active CABGA 28 I Yes Reel Package Info
Availability
97ULP845AHLF Active CABGA 28 C Yes Tray Package Info
Availability
97ULP845AHLFT Active CABGA 28 C Yes Reel Package Info
Availability

Documentation & Downloads

タイトル 他の言語 Type 形式 サイズ 日付
データシート
97ULP845A Datasheet Datasheet PDF 329 KB
PCN / PDN
PDN# : CQ-14-02R2 Product Discontinuation Notice PDF 549 KB
PDN# : CQ-14-02R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 545 KB
PDN# : CQ-14-02 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 544 KB
PCN#: A1309-03 Additional Assembly Sources Product Change Notice PDF 398 KB