For low phase noise outputs, the phase detector frequency of both PLLs should be as high as possible but below 200 MHz. Other optimization criteria include the desired PLL bandwidth and loop filter component selection. Lower phase detector frequencies (1st stage PLL) support lower loop bandwidth values and smaller loop filter components and value.

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8V19N408 Data Sheet Datasheet PDF 849 KB
8V19N407 Data Sheet Datasheet PDF 877 KB