NOTICE - The following device(s) are recommended alternatives:

The 5T93GL16 2.5V differential clock buffer is a user-selectable differential input to sixteen LVDS outputs. The fanout from a differential input to sixteen LVDS outputs reduces loading on the preceding driver and provides an efficient clock distribution network. The 5T93GL16 can act as a translator from a differential HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML, or LVDS input to LVDS outputs. A single-ended 3.3V / 2.5V LVTTL input can also be used to translate to LVDS outputs. The redundant input capability allows for a glitchless change-over from a primary clock source to a secondary clock source. Selectable inputs are controlled by SEL. During the switchover, the output will disable low for up to three clock cycles of the previously-selected input clock. The outputs will remain low for up to three clock cycles of the newly-selected clock, after which the outputs will start from the newly-selected input. A FSEL pin has been implemented to control the switchover in cases where a clock source is absent or is driven to DC levels below the minimum specifications. The 5T93GL16 outputs can be asynchronously enabled/disabled. When disabled, the outputs will drive to the value selected by the GL pin. Multiple power and grounds reduce noise.

特性

  • Guaranteed low skew: <25ps (maximum)
  • Very low duty cycle distortion: <100ps (maximum)
  • High speed propagation delay: <2ns (maximum)
  • Up to 650MHz operation
  • Glitchless input clock switching
  • Selectable inputs
  • Hot insertable and over-voltage tolerant inputs
  • 3.3V/2.5V LVTTL, HSTL, eHSTL, LVEPECL (2.5V), LVPECL (3.3V), CML or LVDS input interfaces
  • Selectable differential inputs to sixteen LVDS outputs
  • Power-down mode
  • At power-up, FSEL should be LOW
  • 2.5V VDD
  • -40°C to 85°C ambient operating temperature
  • Available in VFQFPN package

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete VFQFPN 52 I 是的 Tray
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1403-03 Gold wire to Copper wire 产品变更通告 PDF 42 KB
PDN# : CQ-14-01 (R1) PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 539 KB
PDN# : CQ-14-01 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 538 KB
PCN#: A-0410-02, Change IDT marking logo with new IDT gridless w 产品变更通告 PDF 24 KB
PCN#: A-0412-04 - To comply with Pb-free labels - Green Products 产品变更通告 PDF 80 KB
PCN#: L-0405-04 To comply with current EIA Std 产品变更通告 PDF 143 KB
PCN#: A-0310-01, Green Products 产品变更通告 PDF 26 KB
其他
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB