The 74FCT810T is a dual bank inverting/ non-inverting clock driver built using advanced dual metal CMOS technology. It consists of two banks of drivers, one inverting and one non-inverting. Each bank drives five output buffers from a standard TTL-compatible input. The FCT810T has low output skew, pulse skew and package skew. Inputs are designed with hysteresis circuitry for improved noise immunity. The outputs are designed with TTL output levels and controlled edge rates to reduce signal noise. The part has multiple grounds, minimizing the effects of ground inductance.

特性

  • 0.5 MICRON CMOS Technology
  • Guaranteed low skew < 600ps (max.)
  • Very low duty cycle distortion < 700ps (max.)
  • Low CMOS levels
  • TTL compatible inputs and outputs
  • TTL level output voltage swings
  • High drive: -32mA IOH, +48mA IOL
  • Two independent output banks with 3-state control: – One 1:5 inverting bank – One 1:5 non-inverting bank
  • Available in QSOP, SSOP, and SOIC packages

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete SSOP 20 C 是的 Tube
Availability
Obsolete QSOP 20 C 是的 Tube
Availability
Obsolete SOIC 20 C 是的 Tube
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
其他
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB