NOTICE - The following device(s) are recommended alternatives:

The 8532AY-01 is a low skew, 1-to-17, Differential- to-3.3V LVPECL Fanout Buffer and a member of the family of High Performance Clock Solutions from ICS. The 8532AY-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. Guaranteed output and part-to-part skew characteristics make the 8532AY-01 ideal for those clock distribution applications demanding well defined performance and repeatability.

Features

  • Seventeen differential 3.3V LVPECL outputs
  • Selectable differential CLK, nCLK or LVPECL clock inputs
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
  • PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL
  • Maximum output frequency: 500MHz
  • Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input
  • Output skew: 50ps (maximum)
  • Part-to-part skew: 250ps (maximum)
  • Propagation delay: 2.5ns (maximum)
  • 3.3V operating supply
  • 0°C to 70°C ambient operating temperature
  • Industrial temperature information available upon request

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
8532AY-01LF Obsolete PPG52 TQFP 52 C Yes Tray
Availability
8532AY-01LFT Obsolete PPG52 TQFP 52 C Yes Reel
Availability

Documentation & Downloads

文档标题 他の言語 文档类型 文档格式 文件大小
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN / PDN
PDN# CQ-14-05 MARKET DECLINED PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 192 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site Product Change Notice PDF 36 KB
PCN#: A1309-03 Additional Assembly Sources Product Change Notice PDF 398 KB
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 363 KB
其它
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB

Boards & Kits