The 87158 is a high performance 1-to-6 LVPECL-to- HCSL/LVCMOS ClockGenerator. The 87158 has one differential input (which can accept LVDS, LVPECL, LVHSTL, SSTL, HCSL), six differential HCSL output pairs and two complementary LVCMOS/LVTTLoutputs. The six HCSL output pairs can be individually configured for divide-by-1, 2, and 4 or high impedance by use of select pins. The two complementary LVCMOS/LVTTL outputs can be configured for divide by 2, divide by 4, high impedance, or driven low for low power operation. The primary use of the 87158 is in Intel® E8870 chipsets that use Intel® Pentium 4 processors. The 87158 converts the differential clock from the main system clock into HCSL clocks used by Intel® Pentium 4 processors. However, the 87158 is a highly flexible, general purpose device that operates up to 600MHz and can be used in any situation where Differential-to-HCSL translation is required.

特性

  • Six HCSL outputs
  • Two LVCMOS/LVTTL outputs
  • One Differential LVPECL clock input pair
  • PCLK, nPCLK supports the following input types: LVDS, LVPECL, LVHSTL, SSTL, HCSL
  • Maximum output frequency: 600MHz (maximum)
  • Output skew: 100ps (maximum)
  • Propagation delay: 4ns (maximum)
  • 3.3V operating supply
  • 0°C to 85°C ambient operating temperature
  • Available in both standard and lead-free RoHS compliant packages
  • Industrial temperature information available upon request

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete SSOP 48 C 是的 Tube
Availability
Obsolete SSOP 48 C 是的 Reel
Availability
Obsolete TSSOP 48 C 是的 Tube
Availability
Obsolete TSSOP 48 C 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention 应用文档 PDF 180 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1506-02 Gold wire to Copper wire 产品变更通告 PDF 35 KB
PCN#: A1309-03 Additional Assembly Sources 产品变更通告 PDF 398 KB
PCN# : A1309-01 Changed of Traceability Mark Format 产品变更通告 PDF 439 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
Downloads
87158 IBIS 模型 - IBIS ZIP 171 KB
其他
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB