Dual DDR zero delay buffer

特性

  • High performance, low jitter zero delay buffer
  • I2C for functional and output control
  • Dual bank 1-6 differential clock distribution
  • 2 separate feedback in & out for input to output
  • Synchronization for each bank
  • Supports up to 4 DDR DIMMs
  • Supports up to 533MHz (DDRII 1066)

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete SSOP 48 C 是的 Tube
Availability
Obsolete SSOP 48 C 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : K-13-01R2 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 125 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
PDN# : K-13-01R1 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 125 KB
PDN# : K-13-01 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 122 KB
其他
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB
PC Clocks Contact Info 其它 PDF 62 KB