The MK1716-01 is a versatile serial programmable clock source which takes up very little board space. The device can simultaneously generate two groups of 4 output clocks and a reference clock output. Both clock groups (CLKA and CLKB) are derived from a single PLL, and have the ability to incorporate Spread Spectrum frequency modulation for reduced system EMI. Each group has control of independent PLL output divide values. Outputs may be programmed on the fly, and will lock to a new frequency in 10 ms or less. Each of the two groups are powered by a separate VDDIO voltage. The reference clock uses the fixed VDD voltage. VDDIO may vary from 2.5 V to VDD. The devices includes a OE pin which tri-states the output clocks and when tied low. IDT's VersaClockTM software allows the user to generate MK1716-01 device optimizing configuration code for target output frequencies and spread spectrum amounts.

特性

  • Packaged in 28-pin SSOP
  • Operating voltage 3.3 V
  • Serially programmable: user determines the output frequency via a 3-wire interface
  • Highly accurate frequency generation
  • M/N Multiplier PLL: M = 1..2048, N = 1..1024
  • Eliminates the need for custom Quartz Oscillators
  • Input crystal frequency of 5-27 MHz
  • Input clock frequency of 3-50 MHz
  • Output clock frequencies of 250 kHz to 133.33 MHz
  • Spread Spectrum frequency modulation for reduced system EMI
  • Center or down spread ±0.5% min to 4% total
  • Selectable 32 kHz and 120 kHz modulation rate
  • Advanced, low power, sub-micron CMOS process
  • Separate VDD 's for each bank of 4 outputs
  • Output skew <250 ps within output bank
  • OE control on outputs

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete QSOP 28 C 是的 Tube
Availability
Obsolete QSOP 28 C 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
MK1716-01 Datasheet 数据手册 PDF 263 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products 应用文档 PDF 128 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-837 Overdriving the Crystal Interface 应用文档 PDF 133 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : U-12-03R4 PRODUCT DISCONTINUANCE NOTICE 产品停产通告 PDF 72 KB
PDN# : U-12-03R3 产品停产通告 PDF 72 KB
Downloads
MK1716-01 3.3 V IBIS Model 模型 - IBIS ZIP 3 KB