The IDT6P61033 is an 8-output very low power buffer for 100MHz PCIe Gen1, Gen2 and Gen3 applications with  integrated output terminations providing Zo=100Ω. The device has 8 output enables for clock management, and 3 selectable SMBus addresses.

特性

  • DIF cycle-to-cycle jitter <50ps 
  • DIF output-to-output skew <50ps
  • DIF phase jitter is PCIe Gen1-2-3 compliant
  • Very low additive phase jitter in bypass mode
  • Integrated terminations provide 100Ω differential Zo reduced component count and board space
  • 1.8V operation; minimal power consumption
  • Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings
  • OE# pins; support DIF power management 
  • HCSL compatible differential input; can be driven by common clock sources
  • LP-HCSL differential clock outputs; reduced power and board space
  • Programmable Slew rate for each output; allows tuning for various line lengths
  • Programmable output amplitude; allows tuning for various application environments
  • Pin/software selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Outputs blocked until PLL is locked; clean system start-up
  • Software selectable 50MHz or 125MHz PLL operation; useful for Ethernet applications
  • Configuration can be accomplished with strapping pins; SMBus interface not required for device control
  • 3.3V tolerant SMBus interface works with legacycontrollers 
  • Space saving 48-pin 6x6mm VFQFPN; minimal board space
  •  Selectable SMBus addresses; multiple devices can easily share an SMBus segment

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 封装 Buy Sample
6P61033NDGI Obsolete VFQFPN 48 I 是的 Tray Package Info
Availability
6P61033NDGI8 Obsolete VFQFPN 48 I 是的 Reel Package Info
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
IDT6P61033_freescale Datasheet Datasheet PDF 278 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN / PDN
PDN# : CQ-15-01 (R1) Quarter PDN for Declined Market Product Discontinuation Notice PDF 550 KB
PDN# : CQ-15-01 Quarter PDN for Declined Market Product Discontinuation Notice PDF 547 KB
其他
PCI Express Timing Solutions Overview Overview PDF 275 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB