The 6P61043 is a 4-output very low power buffer for 100MHz PCIe Gen1, Gen2 and Gen3 applications with integrated output terminations providing Zo=100Ω for Freescale Systems. The device has 4 output enables for clock management, and 3 selectable SMBus addresses.

Features

  • Integrated terminations provide differential Zo=100Ω: reduced component count and board space
  • 1.8V operation: minimal power consumption
  • OE# pins: support DIF power management
  • HCSL compatible differential input: can be driven by common clock sources.
  • LP-HCSL differential clock outputs: reduced power and board space
  • Programmable Slew rate for each output: allows tuning for various line lengths.
  • Programmable output amplitude: allows tuning for various application environments.
  • Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
  • Outputs blocked until PLL is locked: clean system start-up
  • Software selectable 50MHz or 125MHz PLL operation: useful for Ethernet Applications
  • Configuration can be accomplished with strapping pins: SMBus interface not required for device control.
  • 3.3V tolerant SMBus interface works with legacy controllers.
  • Space saving 32-pin 5x5mm MLF: minimal board space
  • Selectable SMBus addresses: multiple devices can easily share an SMBus segment.

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
6P61043NLGI Preview NLG32 VFQFPN 32 I Yes Tray
Availability
6P61043NLGI8 Preview NLG32 VFQFPN 32 I Yes Reel
Availability

Documentation & Downloads

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
6P61043 Datasheet_Freescale Datasheet PDF 291 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT?s ?Universal? Low-Power HCSL Outputs Application Note PDF 480 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
其它
PCI Express Timing Solutions Overview Overview PDF 275 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

Boards & Kits