The 9DB436 is a zero delay/fanout buffer for PCI Express™ clocking. It supports PCIe Gen1–3 in zero delay mode and PCIe Gen1–4 in fanout mode. The 9DB436 also features a Safe Power Sequence (SPS) clock input. The 9DB436 is a pin-compatible upgrade to the 9DB433 and 9DB434.


  • Four 0.7V current-mode differential HCSL output pairs
  • PCIe Gen3 jitter < 0.6ps rms in ZDB mode
  • PCIe Gen4 additive jitter < 0.1ps rms in fanout mode
  • SPS internal receiver bias network keeps input clock parked when input is floating
  • Supports both 85Ω and 100Ω output impedance with appropriate resistor selection
  • OE# pins default to controlling outputs
  • Supports zero delay buffer mode and fanout mode
  • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's
  • Spread spectrum compatible
  • Three selectable SMBus addresses


下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 封装 Buy Sample
9DB436AGILF Active TSSOP 28 I 是的 Tube Package Info
9DB436AGILFT Active TSSOP 28 I 是的 Reel Package Info


文档标题 其他语言 类型 文档格式 文件大小 日期
9DB436 Datasheet Datasheet PDF 383 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
9DB436 IBIS Model Model - IBIS ZIP 12 KB
PCI Express Timing Solutions Overview Overview PDF 275 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB