The 9DBL0252 2-output zero-delay/fan-out buffer is a 3.3V member of Renesas' Full-Featured PCIe family. The 9DBL0252 supports PCIe Gen1 through Gen5 and both Common and Independent Reference Clock architectures.

For information regarding evaluation boards and material, please contact your local sales representative.

特性

  • Additive PCIe Gen5 CC jitter < 60fs RMS (fan-out mode)
  • PCIe Gen5 CC jitter < 150fs RMS (High-BW ZDB Mode)
  • 2 Low-Power HCSL (LP-HCSL) outputs eliminate 4 resistors per output pair
  • Direct connection to 85Ω transmission lines
  • Dedicated OE# pin for each output
  • Spread Spectrum tolerant
  • Pin or SMBus configuration
  • 3 selectable SMBus addresses
  • SMBus interface not required for device operation
  • Easy AC-coupling to other logic families, see application note AN-891.
  • Space saving 24-pin 4 × 4 mm VFQFPN

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type 封装 Buy Sample
9DBL0252BKILF Active VFQFPN 24 I 85 Tray Package Info
Availability

Buy / Quote
9DBL0252BKILFT Active VFQFPN 24 I 85 Reel Package Info
Availability
Buy / Quote

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
9DBL02x2-04x2-06x1-08x1 Family Datasheet – Datasheet PDF 486 KB
使用指南与说明
Timing Products for NXP (Freescale) i.MX (Chinese) English Guide PDF 512 KB
Timing Products for NXP (Freescale) i.MX (Chinese) English Guide PDF 512 KB
应用指南 &白皮书
AN-975 Cascading PLLs – Application Note PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs – Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements – Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 442 KB
AN-839 RMS Phase Jitter – Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels – Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced – Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance – Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads – Application Note PDF 121 KB
PCN / PDN
PCN# : TB1912-02(R1) Convert Shipping Media
from Tube or Tray to Cut Reel 		– Product Change Notice PDF 5.71 MB
PCN# : TB1912-02 Convert Shipping Media
from Tube or Tray to Cut Reel 		– Product Change Notice PDF 5.61 MB
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – Product Change Notice PDF 983 KB
Downloads
9DBL02P2 IBIS Model – Model - IBIS IBS 639 KB
其他
PCI Express Timing Solutions Overview – Overview PDF 275 KB
9DBL0242 EVB Reference Schematic – Schematic PDF 71.36 MB
Timing Solutions Products Overview – Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
info: For device-specific or order-specific documentation, submit a support request.

News & Additional Resources

日期
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications 2018年5月21日
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices 2018年4月30日
An Insider’s Guide to Finding the Right Timing Device for Your System 2017年12月18日
Why Fanout Buffers Make More Sense 2017年11月28日
Time for Performance 2017年10月11日
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped 2014年12月18日