The 9DBL0252 device is a 3.3V member of IDT's Full-Featured PCIe family. The 9DBL0252 supports PCIe Gen1-4 Common Clocked (CC) and  PCIe Separate Reference Independent Spread (SRIS) systems. It offers an integrated output termination providing direct connection to 85Ω transmission lines. The 9DBL02P2 can be factory programmed with a user-defined power up default SMBus configuration.

For information regarding evaluation boards and material, please contact your local IDT sales representative.

Features

  • PCIe Gen1-2-3-4 CC compliant in ZDB mode
  • PCIe Gen2 SRIS compliant in ZDB mode
  • Supports PCIe Gen2-3 SRIS in fan-out mode
  • Supports PCIe SRnS clocking in ZDB or fan-out mode
  • Direct connection to 85Ω transmission lines; saves 8 resistors compared to standard PCIe devices
  • Spread Spectrum tolerant; allows reduction of EMI
  • Pin/SMBus selectable selectable PLL bandwidth and PLL Bypass; minimize phase jitter for each application
  • Device contains default configuration; SMBus interface not required for device operation.
  • Easy AC-coupling to other logic families, see IDT application note AN-891.
  • Space saving 24-pin 4x4mm VFQFPN; minimal board space

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Output Impedance Carrier Type Buy Sample
9DBL0252BKILF Active NLG24P3 VFQFPN 24 I , 85 Tray
Availability

Buy / Quote
9DBL0252BKILFT Active NLG24P3 VFQFPN 24 I , 85 Reel
Availability
Buy / Quote

技术资料

文档标题 他の言語 文档类型 文档格式 文件大小 日
数据手册与勘误表
9DBL0242_52 Datasheet – Datasheet PDF 387 KB
使用指南与说明
Timing Products for NXP (Freescale) i.MX ( 简体中文) English Guide PDF 321 KB
应用指南 &白皮书
AN-975 Cascading PLLs – Application Note PDF 255 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT?s ?Universal? Low-Power HCSL Outputs – Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL – Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements – Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection – Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals – Application Note PDF 442 KB
AN-839 RMS Phase Jitter – Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels – Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced – Application Note PDF 160 KB
AN-815 Understanding Jitter Units – Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter – Application Note PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance – Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads – Application Note PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility – Product Change Notice PDF 983 KB
其它
PCI Express Timing Solutions Overview – Overview PDF 275 KB
9DBL0242 EVB Reference Schematic – Schematic PDF 71.36 MB
Timing Solutions Products Overview – Overview PDF 4.11 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

软件与工具

文档标题 他の言語 文档类型 文档格式 文件大小 日
9DBL02P2 IBIS Model – Model - IBIS IBS 639 KB
info: For device-specific or order-specific documentation, submit a support request.

News & Additional Resources

日
Comparing and Contrasting PCIe and Ethernet Clock Jitter Specifications 2018年5月21日
IDT Extends Leadership in Datacenter and Networking Systems with Launch of Its Latest PCI Express Timing Devices 2018年4月30日
An Insider’s Guide to Finding the Right Timing Device for Your System 2017年12月18日
Why Fanout Buffers Make More Sense 2017年11月28日
Time for Performance 2017年10月11日
IDT Surpasses Milestone of 3 Million Low-Power PCIe Gen3 Buffers Shipped 2014年12月18日