The 9DBV0441 is a member of Renesas' SOC-Friendly 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Zo = 100Ω for direct connection to 100Ω transmission lines. The device has 4 output enables for clock management, and 3 selectable SMBus addresses.

特性

  • Direct connection to 100Ω transmission lines; saves 16 resistors compared to standard HCSL outputs
  • 53mW typical power consumption in PLL mode; minimal power consumption
  • Spread Spectrum (SS) compatible; allows use of SS for EMI reduction
  • OE# pins: support DIF power management
  • HCSL compatible differential input: can be driven by common clock sources
  • Programmable slew rate for each output: allows tuning for various line lengths
  • Programmable output amplitude: allows tuning for various application environments
  • Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
  • Outputs blocked until PLL is locked: clean system start-up
  • Software selectable 50MHz or 125MHz PLL operation: useful for Ethernet applications
  • Configuration can be accomplished with strapping pins: SMBus interface not required for device control
  • 3.3V tolerant SMBus interface works with legacy controllers
  • Space-saving 5 × 5 mm 32-VFQFPN: minimal board space
  • Selectable SMBus addresses: multiple devices can easily share an SMBus segment

产品选择

下单器件 ID Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Active 32 I 是的 Tray
Availability
Active 32 I 是的 Reel
Availability
Active 32 C 是的 Tray
Availability
Active 32 C 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
9DBV0441 Datasheet 数据手册 PDF 368 KB
应用指南 &白皮书
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs 应用文档 PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL 应用文档 PDF 235 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-843 PCI Express Reference Clock Requirements 应用文档 PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 产品变更通告 PDF 983 KB
PCN# : A1611-02 Add JCET China as Alternate Assembly and Change of Material Set at Alternate Assembly Location 产品变更通告 PDF 583 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 544 KB
Downloads
9DBV0441 IBIS Model 模型 - IBIS ZIP 70 KB
其他
Clock Distribution Overview 日本語 概览 PDF 217 KB
9DBV0441 Reference Schematic 原理图 PDF 75 KB
PCI Express Timing Solutions Overview 概览 PDF 275 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Fanout Buffers Product Overview 产品简述 PDF 739 KB
High-Performance, Low-Phase Noise Clocks Buffers product brief 产品简述 PDF 378 KB