The 9FGV1008B is a member of IDT's PhiClock™ programmable clock generator family. The 9FGV1008B provides one integer frequency, one copy of a fractional or spread spectrum output frequency, and one copy of the crystal reference input. Two select pins allow for hardware selection of the desired configuration, or two I2C bits allow easy software selection of the desired configuration. The user may configure any one of the four OTP configurations as the default when operating in I2C mode. Four unique I2C addresses are available, allowing easy I2C access to multiple components.


  • 1.8V–3.3V core VDD and VDDREF
  • Individual 1.8V–3.3V VDDO for each output pair
  • Supports HCSL, LVDS and LVCMOS I/O standards
  • HCSL utilizes IDT's LP-HCSL technology for improved performance, lower power and higher integration:
    • Programmable output impedance of 85Ω or 100Ω
  • On-board OTP supports up to 4 complete configurations
  • Configuration selected via strapping pins or I2C
  • Internal crystal load capacitors
  • < 135mW at 1.8V with outputs running at 100MHz (LP-HCSL)
  • 4 programmable I2C addresses: D0, D2, D4, D6
  • Supports LVPECL and CML logic with easy AC coupling – see AN-891 for alternate terminations
  • Supported by IDT Timing Commander™ software
  • Integrated 50MHz crystal option on 9FGV1008Q5
  • Programmable spread spectrum modulation frequency and amount


This device is factory-configurable. Try the Custom Part Configuration Utility.
下单器件 ID Part Status Output Type Output Freq Range (MHz) Supply Voltage (V) Xtal Freq (MHz) Carrier Type 封装 Buy Sample
9FGV1008B000LTGI Active LP-HCSL, LVCMOS, LVDS 10 - 325 1.8, 2.5, 3.3 8 - 50 Tray Package Info
9FGV1008B000LTGI8 Active LP-HCSL, LVCMOS, LVDS 10 - 325 1.8, 2.5, 3.3 8 - 50 Reel Package Info
9FGV1008BQ500LTGI Active LP-HCSL, LVCMOS, LVDS 10 - 325 1.8, 2.5, 3.3 8 - 50 Tray Package Info
9FGV1008BQ500LTGI8 Active LP-HCSL, LVCMOS, LVDS 10 - 325 1.8, 2.5, 3.3 8 - 50 Reel Package Info


文档标题 其他语言 类型 文档格式 文件大小 日期
9FGV1008B_1008BQ Datasheet Datasheet PDF 561 KB
9FGV100x Register Descriptions and Programming Guide Manual - Software PDF 401 KB
应用指南 &白皮书
PCIe Measurement Techniques for Gen5 and Beyond White Paper White Paper PDF 832 KB
AN-1014 Microstrip vs Stripline: Crosstalk and RMS Phase Jitter Application Note PDF 486 KB
AN-1001 Combining PhiClock and 9ZXL1951D for PCIe Gen4/5 Application Note PDF 244 KB
AN-975 Cascading PLLs Application Note PDF 255 KB
AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 307 KB
AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT Universal Low-Power HCSL Outputs Application Note PDF 480 KB
AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 235 KB
AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.90 MB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
Timing Commander Personality File for 9FGV1008 v1.5 Software ZIP 3.90 MB
PCI Express Timing Solutions Overview Overview PDF 275 KB
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB