The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability. The 854S204I is a low skew, high performance dual, programmable 1-to-2 Differential-to-LVDS, LVPECL Fanout Buffer. The PCLKx, nPCLKx pairs can accept most standard differential input levels. With the selection of SEL_OUT signal, outputs can be selected be to either LVDS or LVPECL levels. The 854S204I is characterized to operate from either a 2.5V or a 3.3V power supply. Guaranteed output and bank skew characteristics make the 854S204I ideal for those clock distribution applications demanding well defined performance and repeatability.

Features

  • Two programmable differential LVDS or LVPECL output banks
  • Two differential clock input pairs
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML
  • Maximum output frequency: 3GHz
  • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx inputs
  • Output skew: 15ps (maximum)
  • Bank skew: 15ps (maximum)
  • Propagation delay: 500ps (maximum)
  • Additive phase jitter, RMS: 0.15ps (typical)
  • Full 3.3V or 2.5V supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package
  • Two programmable differential LVDS or LVPECL output banks
  • Two differential clock input pairs
  • PCLKx, nPCLKx pairs can accept the following differential input levels: LVDS, LVPECL, SSTL, CML
  • Maximum output frequency: 3GHz
  • Translates any single ended input signal to LVDS levels with resistor bias on nPCLKx inputs
  • Output skew: 15ps (maximum)
  • Bank skew: 15ps (maximum)
  • Propagation delay: 500ps (maximum)
  • Additive phase jitter, RMS: 0.15ps (typical)
  • Full 3.3V or 2.5V supply modes
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
854S204BGILF Obsolete PGG16 TSSOP 16 I Yes Tube
Availability
854S204BGILFT Obsolete PGG16 TSSOP 16 I Yes Reel
Availability

Documentation & Downloads

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
854S204I DATASHEET Datasheet PDF 1.57 MB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-846 Termination - LVDS Application Note PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 160 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-833 Differential Input Self Oscillation Prevention Application Note PDF 180 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
PCN / PDN
PDN# : CQ-18-03 Product Discontinuance Notice Product Discontinuation Notice PDF 218 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 611 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB
PCN# : TB1403-01 Changed in Carrier Tape, Plastic Reel and Quantity per Reel on TSSOP-14, TSSOP-16 Product Change Notice PDF 663 KB
PCN# : A1309-01 Changed of Traceability Mark Format Product Change Notice PDF 439 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB
Downloads
854S204I IBIS Model Model - IBIS ZIP 137 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB
IDT Fanout Buffers Product Overview Product Brief PDF 739 KB

Boards & Kits