The 8752I is a low voltage, low skew LVCMOS clock generator. With output up to 240MHz, the 8752I is targeted for high performance clock applications. Along with a fully integrated PLL, the 8752I contains frequency configurable outputs and an external feedback input for regenerating clocks with "zero delay".

Dual clock inputs, CLK0 and CLK1, support redundant clock applications. The CLK_SEL input determines which reference clock is used. The output divider values of Bank A and B are controlled by the DIV_SELA0:1, and DIV_SELB0:1, respectively.

For test and system debug purposes, the PLL_SEL input allows the PLL to be bypassed. When HIGH, the MR/nOE input resets the internal dividers and forces the outputs to the high impedance state.

The low impedance LVCMOS outputs of the 8752I are designed to drive terminated transmission lines. The effective fanout of each output can be doubled by utilizing the ability of each output to drive two series terminated transmission lines.

特性

  • Fully integrated PLL
  • 8 LVCMOS outputs, 7Ω typical output impedance
  • Selectable LVCMOS CLK0 or CLK1 inputs for redundant clock applications
  • Input/Output frequency range: 18.33MHz to 240MHz at VCC = 3.3V ± 5%
  • VCO range: 220MHz to 480MHz
  • External feedback for "zero delay" clock regeneration
  • Cycle-to-cycle jitter: 75ps (maximum), (all outputs are the same frequency)
  • Output skew: 100ps (maximum)
  • Bank skew: 55ps (maximum)
  • Full 3.3V or 2.5V supply voltage
  • -40°C to 85°C ambient operating temperature
  • Lead-Free package fully RoHS compliant

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete TQFP 32 I 是的 Tray
Availability
Obsolete TQFP 32 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
8752I Datasheet 数据手册 PDF 267 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : CQ-16-02 Quarter PDN for Declined Market 产品停产通告 PDF 592 KB
PCN# : A1602-01(R1) Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : A1602-01 Add Greatek Taiwan as Alternate Assembly 产品变更通告 PDF 611 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 50 KB
PCN# : A1401-02 Alternate Copper Wire Assembly Site 产品变更通告 PDF 36 KB
PCN# : TB1303-01 Change of Carrier Tape for TQFP-32, TQFP-48 产品变更通告 PDF 472 KB
Downloads
8752I IBIS Model 模型 - IBIS ZIP 67 KB
其他
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB