The 673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled Oscillator (VCO), and two output buffers. One output buffer is a divide by two of the other. Through the use of external reference and VCO dividers (the 674-01), the user can customize the clock to lock to a wide variety of input frequencies. The 673-01 also has an output enable function that puts both outputs into a high-impedance state. The chip also has a power down feature which turns off the entire device. For applications that require low jitter or jitter attenuation, see the MK2069. For a smaller package, see the 663.

Features

  • Packaged in 16 pin SOIC (Pb-free, ROHS compliant)
  • Access to VCO input and feedback paths of PLL
  • VCO operating range up to 120 MHz (5V)
  • Able to lock MHz range outputs to kHz range inputs through the use of external dividers
  • Output Enable tri-states outputs
  • Low skew output clocks
  • Power Down turns off chip
  • VCO predivide to feedback divider of 1 or 4
  • 25 mA output drive capability at TTL levels
  • Advanced, low power, sub-micron CMOS process
  • Single supply +3.3 V or +5 V ±10% operating voltage
  • Industrial temperature range available
  • Forms a complete PLL, using the 674-01
  • For better jitter performance, please use the MK1575

Product Options

下单器件 ID Part Status Pkg. Code Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
673M-01ILF Obsolete DCG16 SOIC 16 I Yes Tube
Availability
673M-01ILFT Obsolete DCG16 SOIC 16 I Yes Reel
Availability
673M-01LF Obsolete DCG16 SOIC 16 C Yes Tube
Availability
673M-01LFT Obsolete DCG16 SOIC 16 C Yes Reel
Availability

Documentation & Downloads

文档标题 他の言語 文档类型 文档格式 文件大小
数据手册与勘误表
673-01 Datasheet Datasheet PDF 79 KB
应用指南 &白皮书
AN-828 Termination - LVPECL Application Note PDF 322 KB
AN-831 The Crystal Load curve Application Note PDF 395 KB
AN-845 Termination - LVCMOS Application Note PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 495 KB
AN-840 Jitter Specifications for Timing Signals Application Note PDF 442 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products Application Note PDF 128 KB
AN-839 RMS Phase Jitter Application Note PDF 233 KB
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 115 KB
AN-834 Hot-Swap Recommendations Application Note PDF 153 KB
AN-832 Timing Budget and Accuracy Application Note PDF 131 KB
AN-830 Quartz Crystal Drive Level Application Note PDF 143 KB
AN-815 Understanding Jitter Units Application Note PDF 565 KB
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.15 MB
AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 136 KB
AN-806 Power Supply Noise Rejection Application Note PDF 438 KB
AN-805 Recommended Ferrite Beads Application Note PDF 121 KB
AN-801 Crystal-High Drive Level Application Note PDF 202 KB
PCN / PDN
PDN# : MM-15-05 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 531 KB
PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB
PCN# A-0607-06 MMT Thailand as Alternate Assembly Facility for PLCC, SOIC 150mil/300mil Product Change Notice PDF 223 KB
其它
Timing Solutions Products Overview Overview PDF 4.11 MB
IDT Products for Radio Applications 日本語 Product Brief PDF 2.34 MB
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB

Boards & Kits