NOTICE - The following device(s) are recommended alternatives:
The 8413S06 is a PLL-based clock generator specifically designed for Cavium Networks Octeon II processors. This high performance device is optimized to generate the processor core reference clock, sRIO, XAUI, SGMII SerDes reference clocks and the clocks for both the Gigabit Ethernet MAC and PHY. The clock generator offers ultra low-jitter, low-skew clock outputs, and edge rates that easily meet the input requirements for the CN63XX and CN68XX series of processors. The output frequencies are generated from a 25MHz external input source or an external 25MHz parallel resonant crystal. The industrial temperature range of the 8413S06 supports telecommunication, networking, and storage requirements.

特性

  • Six selectable 100MHz, 125MHz, 156.25MHz and 312.5MHz
    clocks for sRIO, XAUI, SGMII and HCSL interface levels
  • One 125MHz RGMII clock (QG), LVCMOS/LVTTL interface levels
  • One 50MHz processor core clock (QF), LVCMOS/LVTTL interface levels
  • Two 25MHz QREF clocks, LVCMOS/LVTTL interface levels, 15Ω output impedance
  • Selectable external crystal or differential (single-ended) input source
  • Crystal oscillator interface designed for 25MHz, parallel resonant crystal
  • Differential CLK, nCLK input pair that can accept: LVPECL, LVDS, LVHSTL, HCSL input levels
  • Internal resistor bias on nCLK pin allows the user to drive CLK input with external single-ended (LVCMOS/ LVTTL) input levels
  • Full 3.3V or mixed 3.3V core/2.5V output supply modes, (RGMII output and QREF outputs)
  • Full 3.3V output supply mode, (HCSL and core clock outputs)
  • -40°C to 85°C ambient operating temperature
  • Lead-free (RoHS 6) packaging​

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete VFQFPN 48 I 是的 Tray
Availability
Obsolete VFQFPN 48 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
8413S06 Datasheet 数据手册 PDF 1.42 MB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-845 Termination - LVCMOS 应用文档 PDF 146 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products 应用文档 PDF 128 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-837 Overdriving the Crystal Interface 应用文档 PDF 133 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : CQ-17-04(R1) Product Discontinuance Notice 产品停产通告 PDF 606 KB
PDN# : CQ-17-04 Product Discontinuance Notice 产品停产通告 PDF 599 KB
其他
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB