NOTICE - The following device(s) are recommended alternatives:

The 844003I-04 is a 3 differential output LVDS Synthesizer designed to generate Ethernet reference clock frequencies. Using a 19.44MHz, 20MHz or 25MHz, 18pF parallel resonant crystal, the following frequencies can be generated based on the settings of four frequency select pins (DIV_SELA[1:0], DIV_SELB[1:0]): 625MHz, 622.08MHz, 312.5MHz, 250MHz, 156.25MHz, 125MHz and 100MHz. The 844003I-04 has two output banks, Bank A with one differential LVDS output pair and Bank B with two differential LVDS output pairs. The two banks have their own dedicated frequency select pins and can be independently set for the frequencies mentioned above. The 844003I-04 uses IDT's 3RD generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The 844003I-04 is packaged in a 32-pin VFQFN package.

特性

  • Three LVDS outputs on two banks, Bank A with one LVDS pair and Bank B with 2 LVDS output pairs
  • Using a 19.44MHz, 20MHz, or 25MHz crystal, the two output banks can be independently set for 625MHz, 622.08MHz, 312.5MHz, 250MHz, 156.25MHz, 125MHz or 100MHz
  • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input
  • VCO range: 490MHz to 680MHz
  • RMS phase jitter at 125MHz (1.875MHz – 20MHz): 0.50ps (typical)
  • Full 3.3V output supply mode
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete VFQFPN 32 I 是的 Tray
Availability
Obsolete VFQFPN 32 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
844003I-04 Datasheet 数据手册 PDF 406 KB
Errata# NEN-11-02 数据手册勘误表 PDF 219 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-846 Termination - LVDS 应用文档 PDF 133 KB
AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-803 Crystal Timing Budget and Accuracy for IDT Timing Clock Products 应用文档 PDF 128 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-834 Hot-Swap Recommendations 应用文档 PDF 153 KB
AN-837 Overdriving the Crystal Interface 应用文档 PDF 133 KB
AN-832 Timing Budget and Accuracy 应用文档 PDF 131 KB
AN-836 Differential Input to Accept Single-ended Levels 应用文档 PDF 120 KB
AN-835 Differential Input with VCMR being VIH Referenced 应用文档 PDF 160 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
PCN / PDN
PDN# : CQ-15-05 Market Declined Quarterly PDN 产品停产通告 PDF 623 KB
PCN# : A1509-03 Gold to Copper wire 产品变更通告 PDF 31 KB
其他
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Products for Radio Applications 日本語 产品简述 PDF 2.34 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB