The MK2049-45A is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication. Basic configuration is determined by a Mode/Frequency Selection Table. Loop bandwidth and damping factor are programmable via external loop filter component selection. Buffer Mode accepts a 10 to 50 MHz input and will provide a jitter attenuated output at 0.5 x ICLK, 1 x ICLK or 2 x ICLK. In this mode the MK2049-45A is ideal for filtering jitter from high frequency clocks. In External Mode, ICLK accepts an 8 kHz clock and will produce output frequencies from a table of common communciations clock rates, CLK and CLK/2. This allows for the generation of clocks frequency-locked to an 8 kHz backplane clock, simplifying clock synchronization in communications systems. The MK2049-45A can be dynamically switched between T1, E1, T3, E3 outputs with the same 24.576 MHz crystal. IDT can customize these devices for many other different frequencies. Contact your IDT representative for more details.

特性

  • Packaged in 20-pin SOIC
  • 3.3 V + 5% operation
  • Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E
  • Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50 MHz
  • Locks to 8 kHz + 100 ppm (External mode)
  • Buffer Mode allows jitter attenuation of 10 - 50 MHz input and x1 / x0.5 or x1 / x2 outputs
  • Exact internal ratios enable zero ppm error
  • Output rates include T1, E1, T3, E3, and OC3 submultiples
  • Pb (lead) free package
  • See also the MK2049-34 and MK2049-36

产品选择

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete SOIC 20 I 是的 Tube
Availability
Obsolete SOIC 20 I 是的 Reel
Availability

文档和下载

文档标题 其他语言 类型 文档格式 文件大小 日期
数据手册与勘误表
MK2049-45A Datasheet 数据手册 PDF 155 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-800 Approved VCXO Crystals 应用文档 PDF 150 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
Using IDT's Integrated VCXO Products MAN05 应用文档 PDF 231 KB
PCN / PDN
PDN# : CQ-15-05 Market Declined Quarterly PDN 产品停产通告 PDF 623 KB
PCN# : A1305-01 Gold Wire to Copper Wire 产品变更通告 PDF 148 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
其他
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB
PLL External Loop Filter Calculator 工程 ZIP 19 KB
External Loop Filters Solver 工程 ZIP 22 KB