The MK2069-04 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that features a PLL (Phase-Locked Loop) input reference divider and feedback divider that have a wide numeric range selectable by the user. This enables a complex PLL multiplication ratio that can be used for translation between clock frequency standards. The on-chip VCXO produces a stable, low jitter output clock using a phase detector frequency down to 8 kHz or lower. This means the MK2069-04 can translate between clock frequencies that have a low common denominator, such as the 8 kHz frame clock common with telecom standards. The MK2069-04 also provides jitter attenuation of the input clock and can accept a low input frequency as well. The device is optimized for user configurability by providing access to all major PLL divider functions. No power-up programming is needed as configuration is pin selected. External VCXO loop filter components provide an additional level of user configurability. The MK2069-04 includes a lock detector (LD) output that serves as a clock status monitor. The clear (CLR) input enables rapid synchronization to the phase of a newly selected input clock.


  • Input clock frequency <1 kHz to 170 MHz
  • Output clock frequency of 500 kHz to 160 MHz
  • Clock translation examples: T1 (1.544 MHz) to/from E1 (2.048 MHz) T3 (44.736 MHz) to/from E3 (34.368 MHz) OC-3 (155.52 MHz) to/from T1 (1.544 MHz) CCIR-601 (27 MHz) to/from SMPTE 274M (74.125 MHz)
  • Jitter attenuation of input clock provided by VCXO circuit. Jitter transfer characteristics user configured through external loop filter component selection.
  • Low jitter and phase noise generation.
  • PLL lock status output
  • PLL Clear function allows seamless synchronizing to an altered input clock phase
  • 2nd PLL provides frequency translation of VCXO PLL output (VCLK) to a higher or alternate output frequency (TCLK).
  • Device will free-run in the absence of an input clock based on VCXO frequency.
  • 56-pin TSSOP package
  • Single 3.3 V power supply
  • 5 V tolerant clock input
  • Pb (lead) free package


下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type Buy Sample
Obsolete TSSOP 56 I 是的 Tube
Obsolete TSSOP 56 I 是的 Reel


文档标题 其他语言 类型 文档格式 文件大小 日期
MK2069-04 Datasheet 数据手册 PDF 285 KB
应用指南 &白皮书
AN-828 Termination - LVPECL 应用文档 PDF 322 KB
AN-841 Pullable Crystal Selection and VCXO Tuning 应用文档 PDF 334 KB
AN-831 The Crystal Load curve 应用文档 PDF 395 KB
AN-849 Loop Filter Component Selection for VCXO Based PLLs 应用文档 PDF 218 KB
AN-848 VCXO - Crystal Selection 应用文档 PDF 222 KB
AN-847 VCXO - Absolute Pull Range 应用文档 PDF 155 KB
AN-842 Thermal Considerations in Package Design and Selection 应用文档 PDF 495 KB
AN-840 Jitter Specifications for Timing Signals 应用文档 PDF 442 KB
AN-838 Peak-to-Peak Jitter Calculations 应用文档 PDF 115 KB
AN-839 RMS Phase Jitter 应用文档 PDF 233 KB
AN-830 Quartz Crystal Drive Level 应用文档 PDF 143 KB
AN-827 Application Relevance of Clock Jitter 应用文档 PDF 1.15 MB
AN-815 Understanding Jitter Units 应用文档 PDF 565 KB
AN-802 Crystal-Measuring Oscillator Negative Resistance 应用文档 PDF 136 KB
AN-800 Approved VCXO Crystals 应用文档 PDF 150 KB
AN-801 Crystal-High Drive Level 应用文档 PDF 202 KB
AN-806 Power Supply Noise Rejection 应用文档 PDF 438 KB
AN-805 Recommended Ferrite Beads 应用文档 PDF 121 KB
Using IDT's Integrated VCXO Products MAN05 应用文档 PDF 231 KB
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 596 KB
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location 产品变更通告 PDF 544 KB
PCN# : TB1504-01R1 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 95 KB
PCN# : TB1504-01 Qty per Reel Standardization for Selective Packages 产品变更通告 PDF 50 KB
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products 产品变更通告 PDF 361 KB
PCN# : A1208-01R1 Gold to Copper Wire 产品变更通告 PDF 254 KB
PCN#: TB-0510-05 New Shipping Tube for TSSOP/TVSOP/TSSOP Exposed 产品变更通告 PDF 201 KB
MK2069-04 3.3V IBIS Model 模型 - IBIS ZIP 4 KB
Timing Solutions Products Overview 概览 PDF 4.11 MB
IDT Clock Generation Overview 日本語 概览 PDF 1.83 MB
IDT Clock Distribution Overview 日本語 概览 PDF 3.79 MB
External Loop Filters Solver 工程 ZIP 22 KB
PLL External Loop Filter Calculator 工程 ZIP 19 KB