The 71124 5V CMOS SRAM is organized as 128K x 8. The JEDEC centerpower/GND pinout reduces noise generation and improves system performance. All bidirectional inputs and outputs of the 71124 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation.

Features

  • JEDEC revolutionary pinout (center power/GND) for reduced noise.
  • Equal access and cycle times – Commercial and Industrial: 12/15/20ns
  • One Chip Select plus one Output Enable pin
  • Bidirectional inputs and outputs directly TTL-compatible
  • Low power consumption via chip deselect
  • Available in a 32-pin 400 mil Plastic SOJ packages

Product Options

下单器件 ID Part Status Pkg. Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 封装 Buy Sample
71124S12YG Active SOJ 32 C 是的 Tube Package Info
Availability
71124S12YG8 Active SOJ 32 C 是的 Reel Package Info
Availability
71124S15YG Active SOJ 32 C 是的 Tube Package Info
Availability
71124S15YG8 Active SOJ 32 C 是的 Reel Package Info
Availability
71124S15YGI Active SOJ 32 I 是的 Tube Package Info
Availability
71124S15YGI8 Active SOJ 32 I 是的 Reel Package Info
Availability
71124S20YG Active SOJ 32 C 是的 Tube Package Info
Availability
71124S20YG8 Active SOJ 32 C 是的 Reel Package Info
Availability
71124S20YGI Active SOJ 32 I 是的 Tube Package Info
Availability
71124S20YGI8 Active SOJ 32 I 是的 Reel Package Info
Availability

Documentation & Downloads

文档标题 他の言語 Type 文档格式 文件大小
数据手册与勘误表
71124 Data Sheet Datasheet PDF 87 KB
Downloads
71124 IBIS Model Model - IBIS ZIP 5 KB