DT uses two types of IDT receivers; P type which are labeled PClk/nPCLk and N type, labeled Clk/nCLK. The common mode range of P type receivers is centered at a higher voltage than that of the N type receivers. To simplify AC termination and DC bias for the receivers, place a 100 ohm shunt across the Clk (PClk) and nClk (nPClk) terminals of the clock receiver and letting the internal 51k resistors set the common mode bias exclusively. To see if this AC termination is viable only requires that the common mode bias with the input terminals shorted, since 100 ohms is a short relative to 51k, lies within the common mode range of each of the P and N type receivers. The only case for which the 100 ohm shunt does not work is PClk/nPClk when the positive terminal has a pull down and the inverting terminal has a 51k voltage divider. This case is easily handled by introducing a common mode pull up into the termination. The reason that the positive offset is introduced as common mode is simply that it does not introduce an extra parasitic on one receiver terminal, as would be the case if the external pull up were placed on one of the terminals. Secondly, the common mode placement makes layout easier because the parasitics introduced are common mode. This makes layout of the external pull up non-critical. Refer to application note AN-844 for more details. For other questions not addressed by the Knowledge Base, please submit a technical support request.


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AN-844 Termination - AC Coupling Clock Receivers 应用文档 PDF 170 KB