Brief overview of IDT's zero-delay buffers. Zero-delay buffers (ZDB) are ideal for applications requiring synchronized clocking for FPGAs, CPUs, logic and synchronous memory. Zero-delay buffers are PLL-based devices that regenerate the input clock signal with fanout to drive multiple loads. Most devices allow the delay through the device to be adjusted through an external feedback path. This allows precise control of the timing of the clock signals to the loads. Zero-delay buffers provide a synchronous copy of the input clock at the outputs, usually without frequency translation. Simple frequency translation is possible when a single divider is used for all outputs, including feedback output, to maintain clock synchronization.Presented by Vik Chaudhry, technical marketing manager at IDT. For more information about IDT's rich portfolio of clock IC timing solutions, visit www.idt.com/go/clocks.