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8S89871I - Block Diagram
8S89871I - Pinout

8S89871

1:2 Differential-to-LVPECL Buffer/Divider

The 8S89871 is a high speed Differential-to-LVPECL Buffer/Divider. The 8S89871 has a selectable ÷2, ÷4, ÷8, ÷16 output dividers. The clock input has internal termination resistors, allowing it to interface with several differential signal types while minimizing the number of required external components. The device is packaged in a small, 3mm x 3mm VFQFN package, making it ideal for use on space-constrained boards.

Features

  • Three LVPECL output pairs
  • Frequency divide select options: ÷2, ÷4, ÷8, ÷16 (Bank B)
  • Pass-through output (Bank A)
  • IN, nIN input can accept the following differential input levels: LVPECL, LVDSCML
  • Output frequency: 2.5GHz
  • Bank skew: 40ps (maximum), Bank B
  • Part-to-part skew: 230ps (maximum)
  • Additive phase jitter, RMS: 0.15ps (typical)
  • Voltage supply range: 2.375V to 3.6V
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8S89871ANLGIActiveNLG16VFQFPN16IYesTubeCheck Availability
8S89871ANLGI8ActiveNLG16VFQFPN16IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8S89871I Datasheet Datasheet PDF 939 KB Apr 24, 2012
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
Other
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016