Skip to main content
82P33724 Functional Block Diagram
82P33724 Pin Diagram

82P33724

Port Synchronizer for IEEE 1588 and Synchronous Ethernet

The 82P33724 Port Synchronizer for IEEE 1588 and Synchronous Ethernet provides tools to manage timing references, clock conversion and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE). The device supports up to three independent timing paths for: IEEE 1588 clock generation; SyncE clock generation; and general purpose frequency translation. The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

Features

  • Supports 3 independent timing paths: IEEE 1588, physical layer (SyncE, SONET/SDH, PDH, CPRI/OBSAI) and recovered line clock
  • Phase synchronizes IEEE 1588 TSUs (Time Stamp Units) at network ports with redundant system-wide IEEE 1588 clock and sync pulse pairs: 1PPS (Pulse Per Second) sync pulses
  • Precise 1PPS edge alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • Frequency synchronizes physical layer ports with redundant system-wide frequency references
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Prevents time errors and PHY bit errors with automatic reference switching, optional hitless reference switching and revertive or non-revertive reference switching
  • DPLLs lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI/OBSAI and GNSS frequencies using fractional-N input dividers
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 72 pin QFN package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeCore Voltage (V)Phase Jitter Typ RMS (ps)App Jitter Compliance
12LVPECL, LVDS, LVCMOS0.000001 - 650.0000000.000001 - 650.0000006LVPECL, LVDS, LVCMOS1.80.560

Product Options

Orderable Part IDPart StatusPkg. CodeTemp. GradePb (Lead) FreeCarrier TypeSample & Buy
82P33724NLGActiveNLG72P2CYesTrayCheck Availability
82P33724NLG8ActiveNLG72P2CYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
no-lock
82P33724 Shortform Datasheet Short Form Datasheet PDF 233 KB Apr 4, 2016
locked
82P33724 Datasheet Datasheet PDF 1.30 MB Apr 1, 2016
Apps Notes & White Papers
locked
AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 175 KB Nov 21, 2016
locked
AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 77 KB Oct 27, 2016
locked
AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx Application Note PDF 165 KB Aug 23, 2016
show all (19)
no-lock
AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
no-lock
ITU-T Profiles for IEEE 1588 White Paper PDF 1.17 MB Oct 23, 2015
no-lock
AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
no-lock
AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
no-lock
AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
no-lock
AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
no-lock
AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
no-lock
AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
no-lock
AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 7, 2014
no-lock
AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
no-lock
AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
no-lock
AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
no-lock
AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
no-lock
AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 15, 2014
no-lock
AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
no-lock
AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 15, 2014
PCNs & PDNs
no-lock
PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
no-lock
PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
Other
no-lock
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
no-lock
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
no-lock
Timing Fabric for Next Generation Communications Equipment Overview 简体中文 Overview PDF 474 KB Mar 1, 2016
show all (4)
no-lock
Timing Fabric for Communications Equipment Overview Overview PDF 263 KB Dec 10, 2015

Software & Tools

Title Type Format File Size Datesort icon
no-lock
82P33724 BSDL Model - BSDL TXT 15 KB Jan 16, 2015
no-lock
82P33724 IBIS Model Model - IBIS ZIP 173 KB Dec 11, 2014