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82P33810 Functional Block Diagram

82P33810

Synchronization Management Unit (SMU) for IEEE 1588 and Synchronous Ethernet

The 82P33810 Synchronization Management Unit (SMU) provides tools to manage timing references, clock sources and timing paths for IEEE 1588 and Synchronous Ethernet (SyncE) based clocks. The device supports up to three independent timing paths that control: IEEE 1588 clock synthesis; SyncE clock generation; and general purpose frequency translation. The device supports physical layer timing with Digital PLLs (DPLLs) and it supports packet based timing with Digitally Controlled Oscillators (DCOs). Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces and IEEE 1588 Time Stamp Units (TSUs).

Features

  • SMU allows any IEEE 1588 software, running on an external processor, to control the generation of electical clocks, and to access and control physical layer synchronization
  • Supports Telecom Boundary Clock (T-BC) and Telecom Time Slave Clock (T-TSC) applications per G.8273.2 with physical layer frequency support to the DCOs (Digitally Controlled Oscillator)
  • Physical layer clocks comply with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • System-wide precise 1PPS (Pulse Per Second) time of day alignment is supported with programmable input-to-input, input-to-output and output-to-output phase delays: sub-ns resolution
  • 24 hour time holdover is supported by DCOs with fine frequency resolution (1.7e-16)
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • IEEE 1588 grand master applications are supported by locking to 1 PPS (Pulse Per Second) references from GPS or other GNSS sources
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 144 pin CABGA package

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeCore Voltage (V)Phase Jitter Typ RMS (ps)App Jitter Compliance
13AMI, LVDS, LVPECL, LVCMOS0.000001 - 650.0000000.000001 - 650.00000014AMI, LVDS, LVPECL, LVCMOS1.80.560

Product Options

Orderable Part IDPart StatusPkg. CodeTemp. GradePb (Lead) FreeCarrier TypeSample & Buy
82P33810ABAGActiveBAG144CYesTrayCheck Availability
82P33810ABAG8ActiveBAG144CYesReelCheck Availability
82P33810BAGObsoleteBAG144CYesTrayCheck Availability
82P33810BAG8ObsoleteBAG144CYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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82P33810 Short Form Datasheet Short Form Datasheet PDF 279 KB Apr 6, 2016
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82P33810 Datasheet Datasheet PDF 1.09 MB Mar 30, 2016
Apps Notes & White Papers
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AN-950 82P338XX/9XX Usage of a SYNC Input for Clock Alignment Application Note PDF 175 KB Nov 21, 2016
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AN-888 SMU for IEEE 1588 and Synchronous Ethernet 82P338xx/339xx Register Map Application Note PDF 666 KB Nov 21, 2016
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AN-807 Recommended Crystal Oscillators for NetSynchro WAN PLL Application Note PDF 77 KB Oct 27, 2016
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AN-946 Using a 19.2MHz System Clock with 82P337xx/8xx/9xx Application Note PDF 165 KB Aug 23, 2016
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-901 How to Implement Master/Slave for SETS and SMU Devices on Timing Redundancy Designs Application Note PDF 475 KB Jul 5, 2016
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ITU-T Profiles for IEEE 1588 White Paper PDF 1.17 MB Oct 23, 2015
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AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
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AN-845 Termination - LVCMOS Application Note PDF 62 KB May 13, 2014
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 7, 2014
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AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-806 Power Supply Noise Rejection Application Note PDF 353 KB Jan 15, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
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AN-801 Crystal-High Drive Level Application Note PDF 109 KB Jan 15, 2014
PCNs & PDNs
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PCN# : N1412-01 Die revision change 82P33814, 82P33831, 82P33714, 82P33731, 82P33810 Product Change Notice PDF 40 KB Jan 6, 2015
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
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Timing Fabric for Next Generation Communications Equipment Overview 简体中文 Overview PDF 474 KB Mar 1, 2016
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Timing Fabric for Communications Equipment Overview Overview PDF 263 KB Dec 10, 2015

Software & Tools

Title Type Format File Size Datesort icon
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82P33810 BSDL Model - BSDL TXT 21 KB Jan 16, 2015
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82P33810A IBIS Model - IBIS TXT 1.05 MB Dec 17, 2014