Synchronous Ethernet WAN PLL
The 82V3398 is an integrated, single-chip solution for the Synchronous Equipment Timing Source for Stratum 3, 4E, 4, SMC, EECOption1, EEC-Option2 clocks in SONET / SDH / Synchronous Ethernet equipment, DWDM and Wireless base station. The device consists of a high quality and configurable DPLL to provide system clock for node timing synchronization within a SONET /SDH / Synchronous Ethernet network.
- Integrated single-chip solution for Synchronous Equipment Timing Source, including Stratum 3, 4E, 4, SMC, EEC-Option 1 and EEC-Option 2 Clocks
- Hitless reference switching to minimize DPLL output phase transients
- Programmable input-to-output phase offset adjustment
- Provides 6 output clocks from 1 Hz (1PPS) to 644.53125 MHz
- Provides 6 input clocks from 1 Hz (1PPS) to 625 MHz
- Internal DCO controlled by an external processor for IEEE-1588 clock generation
- Free- Run, Locked and Holdover modes
- Automatic hitless selected input clock switch on clock failure
- 2 kHz, 4 kHz, 8 kHz, or 1PPS frame sync input, 2 kHz, 8 kHz, or 1PPS frame sync output
- Output clocks for BITS, GPS, 3G, GSM, etc.
- PECL/LVDS and CMOS input/output technologies
- Master/Slave feature for system protection against single chip failure
|App Jitter Compliance||Core Voltage (V)||Input Freq (MHz)||Input Type||Inputs (#)||Output Banks (#)||Output Freq Range (MHz)||Output Signaling||Output Type||Output Voltage (V)||Phase Jitter Max RMS (ps)||Phase Jitter Typ RMS (ps)||Prog. Clock||Prog. Interface||Re-bake Conditions|
|Stratum 4E, Stratum 4, SMC, ITU, Telcordia, Stratum 3||3.3||0.000001 - 625.000000||LVPECL, LVDS, LVCMOS, AMI||6||6||0.000001 - 644.531250||LVDS, LVCMOS, AMI, LVPECL||LVDS, LVCMOS, AMI, LVPECL||3.3||0.800||Yes||SPI, I2C||48hrs@125C|