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9DBV0431 - Block Diagram

9DBV0431

4-output 1.8 V PCIe Gen1-2-3 Zero Delay / Fanout Buffer

The 9DBV0431 is a 4-output very low power buffer for 100 MHz PCIe Gen1, Gen2 and Gen3 applications. It can also be used for 50M or 125M Ethernet Applications via software frequency selection. The device has 4 output enables for clock management.

Features

  • 1.8 V operation: minimal power consumption
  • OE# pins: support DIF power management
  • HCSL compatible differential input: can be driven by common clock sources
  • LP-HCSL differential clock outputs: reduced power and board space
  • Programmable slew rate for each output: allows tuning for various line lengths
  • Programmable output amplitude: allows tuning for various application environments
  • Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
  • Outputs blocked until PLL is locked: clean system start-up
  • Software selectable 50 MHz or 125 MHz PLL operation: useful for Ethernet applications
  • Configuration can be accomplished with strapping pins: SMBus interface not required for device control
  • 3.3 V tolerant SMBus interface works with legacy controllers
  • Space-saving 5x5 mm 32-pin VFQFPN: minimal board space
  • Selectable SMBus addresses: multiple devices can easily share an SMBus segment

Product Specification

App Jitter ComplianceCore Voltage (V)Input Freq (MHz)Output Freq Range (MHz)Output Voltage (V)Power Consumption Typ (mW)
PCIe Gen3, PCIe Gen2, PCIe Gen11.830.000000 - 175.00000025.000000 - 170.0000000.865

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
9DBV0431AKILFActiveNLG32P3VFQFPN32IYesTrayCheck Availability
9DBV0431AKILFTActiveNLG32P3VFQFPN32IYesReelCheck Availability
9DBV0431AKLFActiveNLG32P3VFQFPN32CYesTrayCheck Availability
9DBV0431AKLFTActiveNLG32P3VFQFPN32CYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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9DBV0431 Datasheet Datasheet PDF 204 KB Apr 28, 2016
Apps Notes & White Papers
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AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
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AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB Apr 8, 2015
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
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PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
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PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
Other
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IDT PCI Express Solutions Overview 简体中文, 日本語 Overview PDF 945 KB Aug 4, 2016
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
show all (5)
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IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
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High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012

Software & Tools

Title Type Format File Size Datesort icon
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9DBV0431 IBIS Model Model - IBIS ZIP 66 KB Dec 2, 2015

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