Skip to main content
8741004I - Block Diagram
8741004I - Pinout


Differential-to-LVDS/0.7V Differential PCI Express® Jitter Attenuator

The 8741004I is a high performance Differential-to-LVDS/0.7V Differential Jitter Attenuator designed for use in PCI Express®™ systems. In some PCI Express® systems, such as those found in desktop PCs, the PCI Express® clocks are generated from a low bandwidth, high phase noise PLL frequency synthesizer. In these systems, a jitter attenuator may be required to attenuate high frequency random and deterministic jitter components from the PLL synthesizer and from the system board. The 8741004I has 3 PLL bandwidth modes: 200kHz, 600kHz and 2MHz. The 200kHz mode will provide maximum jitter attenuation, but with higher PLL tracking skew and spread spectrum modulation from the motherboard synthesizer may be attenuated. The 600kHz provides an intermediate bandwidth that can easily track triangular spread profiles, while providing good jitter attenuation. The 2MHz bandwidth provides the best tracking skew and will pass most spread profiles, but the jitter attenuation will not be as good as the lower bandwidth modes. Because some 2.5Gb serdes have x20 multipliers while others have x25 multipliers, the 8741004I can be set for 1:1 mode or 5/4 multiplication mode (i.e. 100MHz input/125MHz output) using the F_SEL pins. The 8741004I uses IDT's 3rd Generation FemtoClock® PLL technology to achieve the lowest possible phase noise. The device is packaged in a 24 Lead TSSOP package, making it ideal for use in space constrained applications such as PCI Express® add-in cards.


  • Two LVDS and two 0.7V differential output pairs Bank A has two LVDS output pairs and Bank B has two 0.7V differential output pairs
  • One differential clock input pair
  • CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTLHCSL
  • Output frequency range: 98MHz - 160MHz
  • Input frequency range: 98MHz - 128MHz
  • VCO range: 490MHz - 640MHz
  • Cycle-to-cycle jitter: 35ps (maximum)
  • Full 3.3V operating supply
  • Three bandwidth modes allow the system designer to make jitter attenuation/tracking skew design trade-offs
  • -40°C to 85°C ambient operating temperature
  • Available in lead-free (RoHS 6) package

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8741004BGILFActiveEJG24TSSOP24IYesTubeCheck Availability
8741004BGILFTActiveEJG24TSSOP24IYesReelCheck Availability


Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
ICS8741004I Datasheet Datasheet PDF 430 KB Jan 27, 2016
PCN# : A1606-02 Add Greatek Taiwan as Alternate Assembly Product Change Notice PDF 567 KB Aug 26, 2016
PDN# : N-12-22R2 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 363 KB Jun 14, 2013
PCN# : TB1303-02 Change of Tape & Reel Packing Method for Selective Products Product Change Notice PDF 361 KB Mar 24, 2013
show all (4)
PDN# : N-12-22R1 PRODUCT DISCONTINUANCE NOTICE Product Discontinuation Notice PDF 209 KB Feb 28, 2013
IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

Related Videos

  • 2015-10-19 PCIe Clocking Architectures
  • 2015-10-19 PCIe Common Clock Architecture and its...
  • 2015-10-19 PCIe Separate Reference without Spread Clock...
  • 2015-10-19 PCIe Separate Reference Clock With...