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9FGL699 - Block Diagram
9FGL699 - Pinout

9FGL699

6-output 3.3 V PCIe Gen1-2 Clock Generator

The 9FGL699 is a 6-output low-power clock sythesizer for PCIe Gen2. It runs from a 25 MHz XTAL, provides spread spectrum capability, and has an SMBus for software control of the device.

Features

  • 6 - 100 MHz Differential low power push pull (HCSL compatible) output pairs
  • 32-pin QFN; space-savings
  • Push Pull outputs
  • Low power consumption, reduced component count
  • PCIe Gen2
  • Spread spectrum capability; reduced EMI when needed
  • D2/D3 SMBus Write/Read SMBus address
  • Cycle-to-cycle jitter <125 ps
  • Output-to-output skew < 100 ps
  • Current consumption < 40 mA
  • PCIe Gen2 phase jitter < 3.0 ps RMS

Product Specification

Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Voltage (V)
LP-HCSL100.00000025.0000001LVCMOS, Crystal3.30.8

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
9FGL699AKLFActiveNLG32P3VFQFPN32CYesTrayCheck Availability
9FGL699AKLFTActiveNLG32P3VFQFPN32CYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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9FGL699 Datasheet Datasheet PDF 165 KB Oct 28, 2015
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Errata# : KEN-13-01 Datasheet PDF 65 KB Feb 20, 2013
Apps Notes & White Papers
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AN-828 Termination - LVPECL Application Note PDF 229 KB Jul 5, 2016
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AN-918 Programmable Clocks vs Crystal Oscillators Application Note PDF 221 KB Mar 10, 2016
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AN-891 Driving LVPECL, LVDS, CML, and SSTL Logic with IDT's "Universal" Low-Power HCSL Outputs Application Note PDF 354 KB Dec 10, 2015
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AN-879 Low-Power HCSL vs Traditional HCSL Application Note PDF 150 KB Apr 8, 2015
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AN-843 PCI Express Reference Clock Requirements Application Note PDF 1.81 MB May 13, 2014
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-839 RMS Phase Jitter Application Note PDF 149 KB May 7, 2014
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AN-838 Peak-to-Peak Jitter Calculations Application Note PDF 32 KB May 7, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-835 Differential Input with VCMR being VIH Referenced Application Note PDF 77 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-802 Crystal-Measuring Oscillator Negative Resistance Application Note PDF 52 KB Mar 12, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
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AN-808 PCI Express/HCSL Termination Application Note PDF 54 KB Jan 15, 2014
PCNs & PDNs
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PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
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PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
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PCN# : A1208-01R1 Gold to Copper Wire Product Change Notice PDF 254 KB Dec 21, 2012
Other
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IDT Clock Generation Overview 日本語 Overview PDF 1.83 MB Apr 28, 2016
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016

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