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8SLVD2102I

Dual 1:2, LVDS Output Fanout Buffer

The 8SLVD2102I is a high-performance differential dual 1:2 LVDS fanout buffer. The device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. The 8SLVD2102I is characterized to operate from a 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVD2102I ideal for those clock distribution applications demanding well-defined performance and repeatability. Two independent buffers with two low skew outputs each are available. The integrated bias voltage generators enables easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

Features

  • Two 1:2, low skew, low additive jitter LVDS fanout buffers
  • Two differential clock inputs
  • Differential pairs can accept the following differential input
    levels: LVDS and LVPECL
  • Maximum input clock frequency: 2GHz
  • Output bank skew: 15ps (maximum)
  • Propagation delay: 300ps (maximum)
  • Low additive phase jitter: 200fs, RMS (maximum);
    fREF = 156.25MHz, VPP = 1V, VCMR = 1V,
    Integration Range 10kHz - 20MHz
  • 2.5V supply voltage
  • Maximum device current consumption (IDD): 90mA
  • Lead-free (RoHS 6) 16-Lead VFQFN package
  • -40°C to 85°C ambient operating temperature

Product Specification

Outputs (#)Output TypeOutput Freq Range (MHz)Input Freq (MHz)Inputs (#)Input TypeOutput Banks (#)Core Voltage (V)Output Skew (ps)Additive Phase Jitter Typ RMS (ps)
4LVDS0.000000 - 2000.0000000.000000 - 2000.0000002LVPECL, LVDS22.5400.08

Product Options

Orderable Part IDPart StatusPkg. CodePkg. TypeLead Count (#)Temp. GradePb (Lead) FreeCarrier TypeSample & Buy
8SLVD2102NLGIActiveNLG16VFQFPN16IYesTubeCheck Availability
8SLVD2102NLGI/WActiveNLG16VFQFPN16IYesReelCheck Availability
8SLVD2102NLGI8ActiveNLG16VFQFPN16IYesReelCheck Availability

Documents

Technical Documentation

Title Other Languages Type Format File Size Datesort icon
Datasheets & Errata
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8SLVD2102 Data Sheet Datasheet PDF 351 KB Nov 20, 2015
Apps Notes & White Papers
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AN-844 Termination - AC Coupling Clock Receivers Application Note PDF 82 KB May 13, 2014
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AN-846 Termination - LVDS Application Note PDF 50 KB May 13, 2014
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AN-842 Thermal Considerations in Package Design and Selection Application Note PDF 403 KB May 12, 2014
show all (10)
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AN-840 Jitter Specifications for Timing Signals Application Note PDF 349 KB May 8, 2014
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AN-834 Hot-Swap Recommendations Application Note PDF 67 KB May 6, 2014
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AN-836 Differential Input to Accept Single-ended Levels Application Note PDF 37 KB May 6, 2014
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AN-833 Differential Input Self Oscillation Prevention Application Note PDF 94 KB May 6, 2014
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AN-827 Application Relevance of Clock Jitter Application Note PDF 1.06 MB Apr 24, 2014
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AN-815 Understanding Jitter Units Application Note PDF 476 KB Apr 24, 2014
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AN-805 Recommended Ferrite Beads Application Note PDF 38 KB Jan 15, 2014
PCNs & PDNs
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PCN# : A1511-01(R1) Add SPEL India as Alternate Assembly Location Product Change Notice PDF 596 KB Jan 28, 2016
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PCN# : A1511-01 Add SPEL India as Alternate Assembly Location Product Change Notice PDF 544 KB Nov 13, 2015
Other
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IDT Clock Distribution Overview 日本語 Overview PDF 3.79 MB Apr 25, 2016
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IDT Fanout Buffers Product Overview Product Brief PDF 739 KB Feb 17, 2015
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High-Performance, Low-Phase Noise Clocks Buffers product brief Product Brief PDF 378 KB Aug 14, 2012

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